Quad Core

[fivemack]

Originally Posted by ATH

Yes, but Barcelona/Phenom is based on 65nm. At the end of 2007 Intel should release its Penryn processor, a true quad core based on 45nm technology.

http://www.pcworld.com/article/id,13...l/article.html

'true quad core' is a marketing term invented by AMD. Intel uses two dual-core dice at 65nm, and will use two dual-core dice at 45nm, because it's a little cheaper to manufacture two small dice and put them in an expensive package than to manufacture one large die.

For Prime95-like jobs where there is nothing shared between the four cores, the slightly faster inter-core communications on AMD's chip are irrelevant; generally if you're constrained by inter-core communication latency you've designed your software poorly.

[ATH]

From old QX6700 review: http://techreport.com/reviews/2006q4...0/index.x?pg=1

As a multi-chip package, the QX6700 contains two copies of a relatively well-integrated dual-core design. The two cores on each chip share a 4MB L2 cache between them, complete with dynamic partitioning and the ability to hand off ownership of data from one core to the next. Unfortunately, the integration between the QX6700's two chips is less than ideal.

Although they occupy the same package, their only means of communication is the system's front-side bus. The two chips must coordinate to ensure the sanity of the contents of their respective L2 caches via this bus. That will sometimes mean writing modified data out of one chip's cache into main memory and then reading it back into the other chip's cache—a positively eternal operation in CPU time. Both chips use this same bus to talk with the rest of the system, including main memory and I/O devices. Also, the presence of three electrical loads on the bus—two CPU chips and the core-logic chipset's north bridge—complicates matters.

and from AMD Barcelona preview: http://www.infoworld.com/article/07/...cgd=2007-02-08

Unlike Intel’s Core, Barcelona gives each core dedicated L2 cache, and Barcelona incorporates a redesign that reduces cache latency (access delays). Barcelona adds Level 3 cache, a newcomer to the x86 and a page out of IBM’s POWER playbook. All four CPU cores in a Barcelona socket will share a single master catalog of recently-retrieved data. A three-level cache is a must-have for a multicore CPU, and that becomes obvious when you get a demo that switches L3 on and off.

[R.D. Silverman]

Originally Posted by fivemack

Well, yes; on the other hand, to buy a Q6600 quad-core processor for $530 now when there is universal consensus that the price will be $266 from July 23rd onwards seems other than completely wise. The unknowable future is one thing, the well-trailed roadmap another.

Time is money. An extra $260 is a pittance when you need the capability NOW.
Some of us have larger price elasticities.

[T.Rex]

Originally Posted by fivemack

'true quad core' is a marketing term invented by AMD. Intel uses two dual-core dice at 65nm, and will use two dual-core dice at 45nm, because it's a little cheaper to manufacture two small dice and put them in an expensive package than to manufacture one large die.

For Prime95-like jobs where there is nothing shared between the four cores, the slightly faster inter-core communications on AMD's chip are irrelevant; generally if you're constrained by inter-core communication latency you've designed your software poorly.

Cruelty has done (15th of April) a very interesting and useful measurements with prime95 v25.2, which is multi-threaded, on a Core2Quad running at 3 GHz, with 2048K and 8192K FFTs.
The figure shows that the processor is not scalable. For 8192 FFT, 2 cores give an improvement factor of: 2, while 4 cores gives: 2.6 , meaning that you buy 2 more cores and get only half of one.
I don't know the impact of the multi-threading of 25.2 compared to 4 instances of prime95, due to 4 threads sharing memory, but it should not be so big.
So, wait for the AMD machine to see if AMD's quad cores is better than Intel's (false) quad core. Or build some performance data with 1, 2, 3 and 4 instances of no multi-threaded prime95.

Tony

[S485122]

I have published some benchmarks with two Core2Quad configurations : one with P965 chipset the other with a nVidia 650i chipset. Cruelty's numbers are for a nVidia chipset. In my experience running Prime95 24.14 with an Intel Quad is worth 3 cores. Quad Core and P95 Using the nVidia chipset a Quad is worth 2 cores. All timings relate to LL tests with 1536K FFT.

[Cruelty]

Originally Posted by S485122

Cruelty's numbers are for a nVidia chipset.

Not anymore, I have used i975x platforms for those benchmarks, see here, here and here.

[S485122]

Originally Posted by Cruelty

Not anymore, I have used i975x platforms for those benchmarks.

Ok, the conclusion is then that a QuadCore is worth 3 cores with the P965 chipset, 2.6 with 975 and only 2 cores with the nVidia chipsets. Since memory is the bottleneck, memory capable of running 2:1 that is 8500 or 1067 MHz is a must .

[T.Rex]

Originally Posted by S485122

Since memory is the bottleneck, memory capable of running 2:1 that is 8500 or 1067 MHz is a must .

Bottleneck is memory bus speed ? or memory controlers (one controler for each core instead of sharing one for 2 or 4 cores) ?
T.

[S485122]

As far as I was able to see the bottleneck is the memory controller or bus, I tried a higher FSB speed, keeping the processor speed the same by changing the multiplier and the iteration times increased.

There is only one memory controller and memory bus for the four cores. I suppose the quad Xeons will have the same problem.

I hope for GIMPS sake that AMD does increase its memory bus enough to provide the data rates Prime95 needs in their comming "true Quad".

[T.Rex]

Originally Posted by S485122

There is only one memory controller and memory bus for the four cores. I suppose the quad Xeons will have the same problem.

The AMD "Phenom" has: "integrated DDR2 memory controller, a shared L3 cache, the company's HyperTransport technology links, 128-bit floating point units, separate L2s and L1s for each core". I think Intel memory controler is outside the cores.
T.

[jasong]

Pardon me if this is an ignorant question, I'm not totally sure I understand all of the thread. If Prime95 processes a lot of data(though it becomes unimportant a few hundredths of a second later), and therefore has a bottleneck, would it not be better to seek out a worthy low bandwidth project and strategically distribute that project, along with Prime95, among the cores? I'm thinking, since it's basically two dual-cores on a Core 2 quad chip, each dual-core could have one instance of Prime95 and one instance of a different program.