Core 2 Duo errors?

paulunderwood · 2006-11-14, 00:29

For Core 2 Duo freaks: http://www.intel.com/design/processo...pdt/313279.htm , in particular error AI 39 seems interesting :surprised

Quote:

AI 39.

Cache Data Access Request from One Core Hitting a Modified Line in
the L1 Data Cache of the Other Core May Cause Unpredictable System
Behavior

Problem:
When request for data from Core 1 results in a L1 cache miss, the request is sent to the L2 cache. If this request hits a modified line in the L1 data cache of Core 2, certain internal conditions may cause incorrect data to be returned to the Core 1.

Implication: This erratum may cause unpredictable system behavior.

Workaround: It is possible for the BIOS to contain a workaround for this erratum.

Status: For the steppings affected, see the Summary Tables of Changes.

cheesehead · 2006-11-14, 20:32

So, if I understand correctly, when Core 1 tries to fetch data from an address that:

(a) is not in Core 1's L1 cache, but is in Core 2's L1 cache,

and

(b) is at or near (within the same cache line) an address at which Core 2 has modified the contents recently (i.e., the modified content is in Core 2's L1 cache, but has not yet been written-back to the shared L2 cache),

then Core 1 may receive incorrect data.

- - -

IIRC every IBM 370 mainframe with the capability for 2 CPUs to access a shared RAM memory had a similar limitation, which is why you were supposed to use semaphores (using the "Compare and Swap" instruction [an elaboration of "Test and Set"], and maybe something else) to signal when a shared memory location could be safely referenced by the other CPU.

Ethan Hansen · 2006-11-14, 21:42

Not a serious concern. This is a carryover bug from the Xeon 5100, first reported in June as #AG39. Hitting this requires a specific data patterns, and all released C2D bios versions should have the workaround in place.

cheesehead · 2006-11-16, 00:00

Duo memory access freaks may also be interested in AG18 and AG43.

- - - - -

For IBM 360/370 architecture freaks:

"Case Study: IBM'S SYSTEM/360-370 ARCHITECTURE"

http://acmqueue.com/acmdl/37/Gifford_Spector.pdf

2006-11-14, 20:32	#2
cheesehead "Richard B. Woods" Aug 2002 Wisconsin USA 1111000001100₂ Posts	So, if I understand correctly, when Core 1 tries to fetch data from an address that: (a) is not in Core 1's L1 cache, but is in Core 2's L1 cache, and (b) is at or near (within the same cache line) an address at which Core 2 has modified the contents recently (i.e., the modified content is in Core 2's L1 cache, but has not yet been written-back to the shared L2 cache), then Core 1 may receive incorrect data. - - - IIRC every IBM 370 mainframe with the capability for 2 CPUs to access a shared RAM memory had a similar limitation, which is why you were supposed to use semaphores (using the "Compare and Swap" instruction [an elaboration of "Test and Set"], and maybe something else) to signal when a shared memory location could be safely referenced by the other CPU. Last fiddled with by cheesehead on 2006-11-14 at 20:54 Reason: Googling found the name "Compare and Swap".

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2006-11-14, 21:42	#3
Ethan Hansen Oct 2005 2³·5 Posts	Not a serious concern. This is a carryover bug from the Xeon 5100, first reported in June as #AG39. Hitting this requires a specific data patterns, and all released C2D bios versions should have the workaround in place.

2006-11-16, 00:00	#4
cheesehead "Richard B. Woods" Aug 2002 Wisconsin USA 2²×3×641 Posts	Duo memory access freaks may also be interested in AG18 and AG43. - - - - - For IBM 360/370 architecture freaks: "Case Study: IBM'S SYSTEM/360-370 ARCHITECTURE" http://acmqueue.com/acmdl/37/Gifford_Spector.pdf