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#1 |
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Jul 2004
Nowhere
32916 Posts |
Read this
he main part of ICM that Intel had to make from scratch was how it would work in a multi-core setup. Unlike the K8 from AMD, NetBurst was never designed with something like that in mind and therefore it's implementation was haphazard. ICM looks to rectify this. Now the two cores won't communicate through the bus, but through their own cache. Each core will be connected to 2-4MB of shared L2 cache, and their L1 caches will be linked as well, allowing for massively fast data transfer between the cores. To further add to the efficiency of ICM, the design will feature a 4-issue core as opposed to a 3-issue core, and it will incorporate “Macro-ops fusion”, which is marketing speak for a technology that allows ICM to execute two select x86 instructions per cycle instead of one. Finally, it will be able to calculate SSE instructions twice as fast. The ICM will be Intel's first totally new design in over 6 years, and it will be the conclusion of lessons learned over the last 15 years. Preliminary benchmarks, though Intel-sponsored, showed engineering samples of these new chips absolutely dominating the latest K8 offerings. Set to debut in only a few months, they should reach our computers by the time fall comes around. When that happens, time will only tell what the future of both chip companies will be. However, for now, one can say this: Intel was taught a lesson by AMD on complacency, and the way this architecture is shaping up, Intel appears to have learned that lesson... and many, many others over the years. they will be connected though the caches and will do double time on sse -_- makes a cruncher happy http://hardware.gotfrag.com/portal/story/31847/?spage=1 |
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#2 |
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Apr 2003
Berlin, Germany
16916 Posts |
http://mersenneforum.org/showthread.php?t=5593
And just to clarify for other readers here: ICM = Intel Core Microarchitecture also called NGMA ("Next Generation Microarchitecture") or even just "Core". |
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#3 | |
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∂2ω=0
Sep 2002
República de California
19·613 Posts |
Quote:
{ From the sound of it, Intel is struggling just to come up to the standards of the "Previous generation" in the RISC world when it comes to multicoring - much of the K8's bus technology dating back to the Alpha. As usual, the folks at Intel are much, much better at continually jacking up the clock frequencies on their chips than they are with actually keeping them fed with data. Why do you think there's still such a huge amount of developer time spent writing custom assembly code for Intel chips? Because it's the only way to get halfway-decent performance out of them, that's why. } endgrumble() |
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#4 |
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Jul 2004
Nowhere
809 Posts |
grumblereply(){
if ((grumble==1) || (feellikegrumble==1)){ echo "Thinks that intel is trying to make comeback"; echo "Believes that they are onto something good and new"; echo "Hopes they will keep the celeron brand"; echo "Prays for cheapnesses"; } } grumblereply(); |
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