New Centrino - Benchmark Seems Too Low

[Dresdenboy]

Thank you.

I'm sure the numbers explain the centrino (Banias) performance we've seen in prime95.

It's SSE2 unit acts like a PIII FPU doing the necessary calculations for both SSE2-register halves.

In general it behaves like PIII in nearly all cases with added SSE2.

Also the cache bandwidth is similar.

Here I compare Banias' numbers with a Pentium III:

CPU features:a7e9f9bf     Banias           Pentium III
Unit                  Latency Throghput Latency  Throghput  
ALU                     1.01    0.52	 1.01       0.52
IMUL                    4.00    1.00	 4.00       1.00
ISHIFT                  1.00    1.00	 1.00       1.00
ISHIFT(NetBurst Opt.)   1.01    1.00	 1.01       1.40 (*)
x87 ADD                 3.00    1.05	 3.00       1.00
x87 MUL                 5.00    2.02	 5.00       2.00
MMX ADD                 1.01    0.51	 1.00       1.01 (*)
MMX MUL                 3.00    1.05	 3.00       1.01
SSE Scalar SP ADD       3.00    1.05	 3.00       1.02
SSE Packed SP ADD       3.01    2.05	 3.01       2.05
SSE Scalar SP MUL       4.00    1.01	 4.00       1.02
SSE Packed SP MUL       4.00    2.01	 4.00       2.01
SSE2 Scalar DP ADD      3.00    1.04
SSE2 Packed DP ADD      3.01    2.05
SSE2 Scalar DP MUL      5.00    2.00
SSE2 Packed DP MUL      5.00    4.01
SSE2 Packed INT ADD     1.18    2.01
SSE2 Packed INT MUL     3.01    2.05

And cache bandwidth test (formatted):
Time for reading 128kB from cache using MOVQ:   30760 cycles (4.26 Bytes/cycle)
Time for reading   8kB from cache using MOVQ:    1074 cycles (7.63 Bytes/cycle)
Time for reading 128kB from cache using MOVAPS: 30761 cycles (4.26 Bytes/cycle)
Time for reading   8kB from cache using MOVAPS:  1079 cycles (7.59 Bytes/cycle)

[magicfan241]

here is the third benchmark (an updated version of the first benchmark):

CPU features:a7e9f9bf
 Unit                            Latency  Throghput
ALU                               1.01       0.52
IMUL                              4.00       1.00
ISHIFT                            1.00       1.01
ISHIFT(NetBurst Opt.)             1.01       1.39
x87 ADD                           3.00       1.07
x87 MUL                           5.00       2.01
MMX ADD                           1.01       1.01
MMX MUL                           3.00       1.05
SSE Scalar SP ADD                 3.00       1.05
SSE Packed SP ADD                 3.01       2.05
SSE Scalar SP MUL                 4.00       1.01
SSE Packed SP MUL                 4.00       2.01
SSE2 Scalar DP ADD                3.00       1.05
SSE2 Packed DP ADD                3.01       2.05
SSE2 Scalar DP MUL                5.00       2.00
SSE2 Packed DP MUL                5.00       4.02
SSE2 Packed INT ADD               1.18       2.01
SSE2 Packed INT MUL               3.01       2.05
x87 MUL+ADD                       8.00       2.13
x87 ADD+MUL+ADD                   9.00       2.48
MMX MUL+ADD                       4.00       1.72
MMX ADD+MUL+ADD                   4.38       1.96
SSE Scalar SP MUL+ADD             7.00       2.01
SSE Packed SP MUL+ADD             7.00       2.42
SSE Scalar SP ADD+MUL+ADD         8.01       3.05
SSE Packed SP ADD+MUL+ADD         8.06       4.52
SSE2 Scalar DP MUL+ADD            8.00       2.01
SSE2 Packed DP MUL+ADD            8.00       4.19
SSE2 Scalar DP ADD+MUL+ADD        9.01       3.05
SSE2 Packed DP ADD+MUL+ADD        9.00       4.48
SSE2 Packed INT MUL+ADD           4.00       3.19
SSE2 Packed INT ADD+MUL+ADD       5.15       4.27

hope this helps some