Zen 2 details announced

[maxzor]

All this human effort trying to figure out what a CPU can do when AI could do it much better...

[M344587487]

Damn these supply issues I want some tasty 3900X benchmarks. It seems like they underestimated 3900X demand as the other new SKUs have the usual supply issues but nowhere near to the same extent. I'm expecting worse for the 3950X when it supposedly gets launched in September, which will be competing with Epyc for the well-binned 8 core chips.


Speaking of the 16 core chips, that's almost certainly going to be an issue with dual channel memory. Are there any recommended ancillary GIMPS/prime programs that run mainly from L2 cache that can soak up the remaining compute available?

[Mysticial]

Originally Posted by M344587487

Damn these supply issues I want some tasty 3900X benchmarks. It seems like they underestimated 3900X demand as the other new SKUs have the usual supply issues but nowhere near to the same extent. I'm expecting worse for the 3950X when it supposedly gets launched in September...

And there's an unknown # of people like me who are holding out for the 3950X. It's probably gonna be a mad rush and I'll definitely be pre-ordering. Reminds of the Skylake X launch 2 years ago. Had I not pre-ordered, I wouldn't have gotten the chip for several more weeks.

I'm also keeping an eye on the 32GB DIMM situation. Those also just launched and also can't stay in stock. But the ones that I want (higher speed + RGB) aren't available yet.

... which will be competing with Epyc for the well-binned 8 core chips.

I'm also waiting to see if AMD throws a curve ball with AVX512 on the TR or Epyc. While Ryzen doesn't have AVX512, AMD declined to confirm it was absent all of Zen 2.

[mackerel]

Originally Posted by M344587487

It seems like they underestimated 3900X demand as the other new SKUs have the usual supply issues but nowhere near to the same extent.

I'd speculate this is a problem born from AMDs marketing position. They want to show a progression of boost clocks up the range, and it gets more difficult to bin enough of those chiplets, while at the same time saving the even better ones for eventual 3950X.

I've heard but not confirmed that the 3900X has one higher binned chiplet than the other. This makes sense as far as boost applies more so at lower active core counts.

Are there any recommended ancillary GIMPS/prime programs that run mainly from L2 cache that can soak up the remaining compute available?

At <64k FFT sizes you can look for tiny primes with LLR/PFGW/genefer. I'm wondering if sieves are a suitable task but I'm not sure how these work. They usually do benefit greatly from HT/SMT.

Originally Posted by Mysticial

But the ones that I want (higher speed + RGB) aren't available yet.

The lack of RGB is probably not helping in my attempts at setting speed records

[hansl]

Originally Posted by Mysticial

I'm also keeping an eye on the 32GB DIMM situation. Those also just launched and also can't stay in stock. But the ones that I want (higher speed + RGB) aren't available yet.

Don't the higher densities mean higher rank, and generally more latency?

[Mysticial]

Originally Posted by hansl

Don't the higher densities mean higher rank, and generally more latency?

Correct, but I value capacity more than latency.

For my purposes, the order of importance is:

1. Total capacity.
2. Memory frequency. (bandwidth)
3. Memory timings. (latency)

[nordi]

Originally Posted by M344587487

Are there any recommended ancillary GIMPS/prime programs that run mainly from L2 cache that can soak up the remaining compute available?

You can use mprime to do ECM on small exponents. Exponents up to ~3,000,000 should fit into the 512kB of L2 cache (stage 2 of ECM uses some RAM bandwidth, but accounts only for ~30% of execution time). You can get assignments from mersenne.org's manual assignment page.

[M344587487]

Originally Posted by Mysticial

...
I'm also waiting to see if AMD throws a curve ball with AVX512 on the TR or Epyc. While Ryzen doesn't have AVX512, AMD declined to confirm it was absent all of Zen 2.

That would be a curveball. They all use the same chiplets so the main reason it would be absent from Ryzen 3000 is that as a consumer part they'd want to guarantee stock clocks were high enough to satisfy a general audience. Even if TR and Epyc parts come out that do support AVX512 (maybe even a microcode update for Ryzen enabling it), I wouldn't believe it's a fully fledged implementation until benchmarks confirm it. If anything it's more realistic to expect that even if AVX512 does appear it'll mainly be via doubled AVX2 (like they did supporting AVX2 with doubled AVX on zen) so the gains will be a minimal improvement to instruction density and whatever benefit that may bring. Proper AVX512 smells more like a zen3 thing but I'd love to be proved wrong.

Originally Posted by mackerel

I'd speculate this is a problem born from AMDs marketing position. They want to show a progression of boost clocks up the range, and it gets more difficult to bin enough of those chiplets, while at the same time saving the even better ones for eventual 3950X.

Releasing on the 7th of July was a big part of their marketing which may have taken priority over trivial things like supply.

Originally Posted by mackerel

I've heard but not confirmed that the 3900X has one higher binned chiplet than the other. This makes sense as far as boost applies more so at lower active core counts.

I don't know if it's intentional, probably not, but it is possible to have a higher binned chip. It's possible that the two CCX's on the same chip clock differently. These chips already self-boost to get the most out of themselves out of the box (acting much more like GPUs do than what we expect of CPUs), but one of the recommended ways I've seen to try and overclock beyond that is to do it on a CCX basis. This video shows a manually overclocked 3900X with a 150 MHz disparity between the highest and lowest CCX (4490, 4441, 4341, 4341, the chiplets do clock quite differently but this is a sample size of 1): https://www.youtube.com/watch?v=M5pHUHGZ7hU&t=45

Thanks for the program suggestions.

[Mysticial]

Originally Posted by M344587487

That would be a curveball. They all use the same chiplets so the main reason it would be absent from Ryzen 3000 is that as a consumer part they'd want to guarantee stock clocks were high enough to satisfy a general audience. Even if TR and Epyc parts come out that do support AVX512 (maybe even a microcode update for Ryzen enabling it), I wouldn't believe it's a fully fledged implementation until benchmarks confirm it. If anything it's more realistic to expect that even if AVX512 does appear it'll mainly be via doubled AVX2 (like they did supporting AVX2 with doubled AVX on zen) so the gains will be a minimal improvement to instruction density and whatever benefit that may bring. Proper AVX512 smells more like a zen3 thing but I'd love to be proved wrong.

I don't think anybody is expecting it to have native AVX512. It doesn't need to anyway since there's a lot more to AVX512 than just the 512-bit width.

[M344587487]

Originally Posted by Mysticial

I don't think anybody is expecting it to have native AVX512. It doesn't need to anyway since there's a lot more to AVX512 than just the 512-bit width.

I didn't realise, it appears that AVX512 has a load of optional extras. If the wiki page is to be believed the Ice Lake chips could be interesting not just for the fabled 10nm. Does anything jump out as particularly useful?

[Mysticial]

Originally Posted by M344587487

I didn't realise, it appears that AVX512 has a load of optional extras. If the wiki page is to be believed the Ice Lake chips could be interesting not just for the fabled 10nm. Does anything jump out as particularly useful?

Off the top of my head, the non-width related things that I've already found useful are:

• 32 registers
• 64-bit arithmetic right shift.
• 64-bit unsigned comparison.
• double <-> int64 conversion (AVX512-DQ)
• Built-in masking.
• Fault-suppressing masked load/store.
• 2-vector permute.
• 16-bit granular permute. (AVX512-BW)
• 8-bit granular permute. (AVX512-VBMI)
• vpmullq (AVX512-DQ)
• valignd/q
• vpternlog
• vrndscale
• Integer FMA (AVX512-IFMA)
• Scatter
• 64-bit min/max
• 14-bit reciprocal
• Bitwise rotate.
• Embedded rounding for FP.

I haven't really tried to use the Sunny Cove/Ice Lake stuff yet. But the things that stand out and may be useful for my purposes are:

• Double vector shifts. (AVX512-VBMI2)
• Galois Field. (AVX512-GFNI)