LLR can't find all L1 cache

vasyannyasha · 2017-12-18, 15:59

I have AMD Athlon X4 860K with L1=16*4+96*2=256 KB
But LLR write
L1 cache size : 16 KB
Could somebody explain this?
pre-thanks

VBCurtis · 2017-12-18, 16:30

In your calculation shown, what label does 16 have? What label does 96 have? (For example, instruction cache or data cache)

Why do you multiply by 4 or 2?

Finally, now that you've labeled those items, why would a program only note one of the 16s, and none of the 96s?

I wager you'll learn a fair bit about what cache does when you read about the answers to these questions.

vasyannyasha · 2017-12-18, 16:56

L1 D(Data?)=16KB *4
L1 I(intsructions?)=96KB*4

VictordeHolland · 2017-12-18, 21:13

L1 is not shared between cores, so why multiply it by 4 (cores)?

kladner · 2017-12-18, 21:30

Quote:

Originally Posted by vasyannyasha

I have AMD Athlon X4 860K with L1=16*4+96*2=256 KB
But LLR write
L1 cache size : 16 KB
Could somebody explain this?
pre-thanks

P95 and CPUZ report a 6700K as L2=256K. My understanding is that this value is 'per core'. With my previous AMD '8 core' CPU, I think P95 reported L2 per '2-ALU + 1 FPU' unit.

Prime95 · 2017-12-19, 00:15

Quote:

Originally Posted by vasyannyasha

I have AMD Athlon X4 860K with L1=16*4+96*2=256 KB
But LLR write
L1 cache size : 16 KB
Could somebody explain this?

Don't worry about it. If LLR is mis-reporting cache sizes it will not affect its operation.

vasyannyasha · 2017-12-19, 07:18

Cpu-Z write
L1-D=16Kb*4
L1-I=96Kb*2(in previous message i wrote 96Kb*4. Sorry, my mistake. In first message everything is right)
L2=2048Kb
So L2 per core=2048/4=512Kb

2017-12-18, 15:59	#1
vasyannyasha "Vasiliy" Apr 2017 Ukraine 3²·7 Posts	LLR can't find all L1 cache I have AMD Athlon X4 860K with L1=164+962=256 KB But LLR write L1 cache size : 16 KB Could somebody explain this? pre-thanks

2017-12-19, 07:18	#7
vasyannyasha "Vasiliy" Apr 2017 Ukraine 63₁₀ Posts	Cpu-Z write L1-D=16Kb4 L1-I=96Kb2(in previous message i wrote 96Kb4. Sorry, my mistake. In first message everything is right) L2=2048Kb So L2 per core=2048/4=512Kb Last fiddled with by vasyannyasha on 2017-12-19 at 07:19 Reason: About mistake in previous message*

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2017-12-18, 16:30	#2
VBCurtis "Curtis" Feb 2005 Riverside, CA 16DE₁₆ Posts	In your calculation shown, what label does 16 have? What label does 96 have? (For example, instruction cache or data cache) Why do you multiply by 4 or 2? Finally, now that you've labeled those items, why would a program only note one of the 16s, and none of the 96s? I wager you'll learn a fair bit about what cache does when you read about the answers to these questions.

2017-12-18, 16:56	#3
vasyannyasha "Vasiliy" Apr 2017 Ukraine 3²·7 Posts	L1 D(Data?)=16KB 4 L1 I(intsructions?)=96KB4

2017-12-18, 21:13	#4
VictordeHolland "Victor de Hollander" Aug 2011 the Netherlands 1179₁₀ Posts	L1 is not shared between cores, so why multiply it by 4 (cores)?