Intel Says It Will Move Away From 'Tick-Tock' Development Cycle

[aurashift]

https://hardware.slashdot.org/story/...elopment-cycle

[Madpoo]

Originally Posted by aurashift

https://hardware.slashdot.org/story/...elopment-cycle

I read that yesterday or today too... But then I remember reading about Kaby Lake last week and thinking "where did that come from?" They snuck in an extra codename when I wasn't looking.

People had wondered how they could keep up the pace with die-shrinks taking much more to accomplish now that we're near the physical limits of silicon. I guess a longer iteration between full cycles was overdue.

[tServo]

What do they think the current limit is, 7 nm or thereabouts? At that size, do quantum effects start to make the state of a gate indeterminate?

[Madpoo]

Originally Posted by tServo

What do they think the current limit is, 7 nm or thereabouts? At that size, do quantum effects start to make the state of a gate indeterminate?

Off the top of my head, I seem to recall reading something lately about 7nm being equal to a trace that's only 20 silicon atoms wide.... looking it up...

Well, I found an old article (amusingly titled "Is 14nm the end of the road for silicon chips?") from 2011. It mentions an atom width for Si at 0.2nm meaning 7nm traces would be 35 atoms wide. Well... whatever the case, it's pretty small.

I won't pretend to know the minimum amount of atoms wide you would need to ensure a reliable connection at some given voltage, but if the smart folks are saying 7nm is really about it, I'll believe them.

Sounds like GaAs (or with Indium in the mix) is the way to get even smaller, but it explains why Intel and others have looked at other ways to increase density besides die shrinks... as in stacking/layering/3D.

I actually just read something when looking at it that suggested Intel might actually only go to 10nm with silicon and 7nm would be InGaAs. Article from last year so maybe things changed since then.

Heck, I just saw an article from 2014 talking about SiGe (silicon-germanium) being a possibility for 7nm, so it just goes to show that things change from year to year on what people think the future will hold.

[CRGreathouse]

Let's look at ultimate physical limits for a moment. According to this paper, the covalent radius of a silicon atom is 1.11(3) Å, giving a width of 0.222(3) nm. An electron has, well, 1 eV of energy and mass \(m_e\); knowing the "height" (energy!) presented by a silicon barrier would allow the calculation of the attenuation factor and hence the tunneling probability. Boldly using numbers I see in this paper (because I have no idea what this means!) I see numbers around 3 eV. This gives these tunneling probabilities for a single-atom barrier based on the "height":

1 eV: 100%
2 eV: 10%
3 eV: 4%
4 eV: 2%
5 eV: 1%
10 eV: 0.1%

Doubling the thickness to two atoms:
2 eV: 1%
3 eV: 0.2%
4 eV: 0.04%

These are all bad of course, but not out of the question depending on the the height (with aggressive error correction). In any case the probability drops off exponentially with height.

Does anyone know what kind of height would be reasonable in a problem like this? That might be enough to find an optimal error correction level which in turn gives true physical limits of silicon. (Other atoms would be similar in width, so difference in height would be the main difference.)

[E_tron]

No more free lunch. Dennard scaling gave out 12 years ago (bringing the era of multi core and complicated out of order pipeline designs) and Morse Law gave out ~3 years ago (no more free transistors).