P4 Prescott - 31 Stage Pipeline ? Bad news for Prime95?

[Dresdenboy]

Originally Posted by Dresdenboy

The long pipeline causes really high latencies for SSE2 instructions (compared to Northwood).

Correction: I forgot, that the new version of this measuring tool adds a lot of latency/throughput results for combined instructions, so the high times at the end misled me a bit The actual SSE2 instruction latencies just increased by 1. But that is additionally to increased L1 and L2 latencies.

[SalemTheCat100]

Originally Posted by Angular

I have been reading the new Prescott reviews with a bit of shock. I expected the prescott doubles both the L1 and L2 cache. The biggest surprise to me is that the integer pipeline increased from 21 stages to 31 stages. This compares to the 10/15 stage (integer/FP) pipeline of the Athlon XP. I am not an assembly programmer but this sounds like it could be trouble for Prime95's highly optimized asm code. Given the market dominance of Intel it may be more critical to fix this problem (if it exists) than to fix the Operteron.

Here we go again. If it's an Intel problem then drop anything that might be of value to Prime95 contributors who happen to be using AMD processors.

Keep doing that and maybe there won't be any AMD Prime95 contributors left.

SALEM

[db597]

Can't remember where I first saw these numbers, but someone did some benchmarks and found that the Prescott finally overtakes the Northwood at around 3.7Gig. That's for overall performance, no idea about for Prime95 specifically.

IMHO, reason for the overtake seems to be the cache size. At over 3.7Gig, the memory and bus can't keep up, so the bigger cache allows the Prescott to pull ahead. It's got nothing to do with Prescotts new pipeline or design though - which will forever be worse at no matter what clockspeed.

And if you're overclocking, the Prescott will take even longer to overtake the Northwood. When I say overclock, I'm thinking about 2.4Gig northwoods being run at 3gig with 1000MHz FSB and 500MHz DDR (lots of enthusiasts seem to have this). In such a case, it will be well over 4GHz before Prescott will catch up with Northwood.

Also, don't count on compiler optimisations to do much to help prescott. Though some might argue that speed will increase as software gets optimised for the new 31 stage pipeline, it won't. There's some results on ixbt using an optimised intel fortran compiler (-xP switch) :

http://www.ixbt.com/cpu/insidespeccpu2000-part-e.shtml

As you can see, using the optimised compiler, Prescott only benefits by more than 1% in 2 out of the 14 benchmarks. And of those 2, 1 improvement is very marginal (191.fma3d). The other is about 15% (168.wupwise). This is possibily due to the use of SSE3.

Until we get into 4GHz+ territory, there's no point to get a Prescott. And this won't happen until earliest Jaunary next year when E0 stepping Prescotts hit the shops - should run cooler as well. But what's worse, a 4GHz+ Prescott will need a LGA775 board with DDR2 and PCI Express. So you're looking at changing your entire setup, not just a simple upgrade. Even the casing will be changing to the BTX format to enable better cooling for the nearly 100W that Prescott will generate. I just don't see Intel doing 4GHz+ on Socket 478, they can't cool it enough.

[ATH]

I got a prescott 3.4 Ghz processor. No matter what priority I set Prime95 at, it only uses 50% CPU, any ideas? Also Prime95 has found L2 cache correct at 1024kb but have Unknown at L1 cache, is that important?

[JuanTutors]

Originally Posted by ATH

I got a prescott 3.4 Ghz processor. No matter what priority I set Prime95 at, it only uses 50% CPU, any ideas? Also Prime95 has found L2 cache correct at 1024kb but have Unknown at L1 cache, is that important?

About the 50% thing, look in http://www.mersenneforum.org/showthread.php?t=3064. I don't know about the rest of the stuff.

[moo]

u proibly have ht enabled its not bad read around the forums theres a lot on it there.

[RickC]

A multi-page article with many benchmarks:

http://tech-report.com/reviews/2004q1/p4-prescott/

Here's an interesting quote from page 2 of the article:

"Five new instructions for complex arithmetic allow for better handling of tasks like Fast Fourier Transforms; these instructions should enhance the Pentium 4's potential in scientific and distributed computing scenarios."


I also found the "Prescott New Instructions Software Developer’s Guide":

http://www.intel.com/cd/ids/develope...tion/66756.htm

The htm page has a link to the pdf.

I'm a software engineer with a rusty math degree but I don't know assembler.

[ET_]

Originally Posted by RickC

A multi-page article with many benchmarks:

http://tech-report.com/reviews/2004q1/p4-prescott/

Here's an interesting quote from page 2 of the article:

"Five new instructions for complex arithmetic allow for better handling of tasks like Fast Fourier Transforms; these instructions should enhance the Pentium 4's potential in scientific and distributed computing scenarios."


I also found the "Prescott New Instructions Software Developer’s Guide":

http://www.intel.com/cd/ids/develope...tion/66756.htm

The htm page has a link to the pdf.

I'm a software engineer with a rusty math degree but I don't know assembler.

SSE3 instructions have been deeply studied by George Woltman and the people involved in Prime95 developing.

They sadly reported here in the forum that SSE3 registers and instructions are of little or no use to enhance Prime95 throughput.

Luigi