Bitcoin miner for GIMPS...

[Batalov]

Originally Posted by ewmayer

[Hint: put down the shovel.]

Woosh!...

Originally Posted by ewmayer

[Hint-which-will-surely-be-ignored: Fundamentally quadratic complexity versus subquadratic.]

Woosh!...

[chalsall]

Originally Posted by Batalov

Woosh!...

Please forgive him. He's Canadian.

[ewmayer]

I suppose a national anthem whose wording opens with "Oh, Canada! We stand on cars and freeze..." is rather a big tip-off, innit?

[Batalov]

Originally Posted by chalsall

Please forgive him. He's Canadian.

I don't think that's right. I am pretty sure that he is ex-Austrian-American.

[chalsall]

Originally Posted by ewmayer

I suppose a national anthem whose wording opens with "Oh, Canada! We stand on cars and freeze..." is rather a big tip-off, innit?

Right, eh?

[science_man_88]

Originally Posted by ewmayer

I suppose a national anthem whose wording opens with "Oh, Canada! We stand on cars and freeze..." is rather a big tip-off, innit?

you are already on the 7th line by the time something even remotely close sounding comes up. I was going to go over potential structure we could use but what ever.

[mancoast]

Originally Posted by ewmayer

so to multiply a pair of GIMPS-wavefront-sized inputs, we simply need to do 70-million-or-so 70-million-bit-wide shift-and-adds ...

So we expand this VHDL to 70 million? We are gonna need a supercomputer for ModelSim.

-- Project Step 8 - Integrating Register and ALU in a datapath
--
-- NAME:Rob Pancoast
--
-------------------------------------------------------------------------------
-- BE SURE TO TURN IN ALL CODE USED!!!
-------------------------------------------------------------------------------
--  Enter ENTITY/ARCHITECTURE for datapath here.
--  (you can use the package that you used in step 6 which
--   should still be in the library)
-------------------------------------------------------------------------------

package step8_package is

  TYPE operations IS (op_A,op_B,op_notA,op_notB,op_AxorB,op_AorB,op_AandB,
                    op_AnandB,op_AxnorB,op_0,op_1,op_incA,op_incB,op_decA,
                    op_decB,op_negA,op_negB,op_AplusB,op_AplusBwC,
                    op_AminB,op_AminBwC,op_BminA);		
end step8_package;

 package body step8_package is
 end step8_package;
 
LIBRARY  IEEE;
USE work.step8_package.all;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY alu_16std_logic IS
      PORT ( alu_op : IN operations;
                  a,b   : IN std_logic_vector(15 downto 0);
                  Cin   : IN std_logic;
                  Zout  : INOUT std_logic_vector(15 downto 0);
                  Cout,n,Z : OUT std_logic);
 END alu_16std_logic;
 
ARCHITECTURE ALU16std_logicpwn OF alu_16std_logic IS
  	PROCEDURE binadd (l,r : IN std_logic_vector;
					  cin : IN std_logic;
					  sum : OUT std_logic_vector;
					  cout : OUT std_logic);
  	PROCEDURE binadd (l,r : IN std_logic_vector;
					  cin : IN std_logic;
					  sum : OUT std_logic_vector;
					  cout : OUT std_logic) IS
	VARIABLE carry : std_logic; --internal variable carry
	BEGIN
		carry := cin;
	FOR i IN l'reverse_range LOOP
		IF (l(i)='0' and r(i)='0' and carry='0') THEN  -- case for 0
			sum(i):='0';
			carry:='0';
		ELSIF ((l(i)='1' and r(i)='0' and carry='0') or (l(i)='0' and r(i)='1' and carry='0') or (l(i)='0' and r(i)='0' and carry='1')) THEN  -- case for 1
			sum(i):='1';
			carry:='0';
		ELSIF ((l(i)='1' and r(i)='1' and carry = '0') or (l(i)='1' and r(i)='0' and carry='1') or (l(i)='0' and r(i)='1' and carry='1')) THEN  -- case for 2
			sum(i):='0';
			carry:='1';
		ELSE   --case for 3
			sum(i):='1';
			carry:='1';
		END IF;
	END LOOP;
    cout := carry;
	end binadd;
	
	 PROCEDURE neg (num : IN std_logic_vector;
					  negnum : OUT std_logic_vector;
					  pcout : OUT std_logic);	 
	PROCEDURE neg (num : IN std_logic_vector;
					  negnum : OUT std_logic_vector;
					  pcout : OUT std_logic) IS
	BEGIN
	-- invert num, add it to 0 with Cin =1
	binadd(not(num),(not num and num),'1',negnum,pcout);
	end neg;	 

					  
	 PROCEDURE binsub (numero,subtractness : IN std_logic_vector;
					  brwin : IN std_logic;
					  sum : OUT std_logic_vector;
					  brwout : OUT std_logic);		
	 PROCEDURE binsub (numero,subtractness : IN std_logic_vector;
					  brwin : IN std_logic;
					  sum : OUT std_logic_vector;
					  brwout : OUT std_logic) IS
	VARIABLE brw : std_logic; --internal variable carry
	VARIABLE concat : std_logic_vector  (2 downto 0);
	BEGIN
		brw := brwin;
	FOR i IN numero'reverse_range LOOP
		concat:= numero(i) & subtractness(i) & brw;
		CASE  concat  IS
			WHEN "000" =>  sum(i):= '0';  brw:= '0'; --0-(0 + 0)
			WHEN "001" =>  sum(i):= '1';  brw:= '1'; --0-(0+1)
			WHEN "010" =>  sum(i):= '1';  brw:= '1'; --0-(1+0)
			WHEN "011" =>  sum(i):= '0';  brw:= '1'; --0-(1+1)
			WHEN "100" =>  sum(i):= '1';  brw:= '0'; --1-(0+0)
			WHEN "101" =>  sum(i):= '0';  brw:= '0'; --1-(0+1)
			WHEN "110" =>  sum(i):= '0';  brw:= '0'; --1-(1+0)
			WHEN "111" =>  sum(i):= '1';  brw:= '1'; --1-(1+1)
			WHEN OTHERS         =>  NULL;
		END CASE;
	END LOOP;
    brwout := brw;
	end binsub;	
BEGIN
	
     PROCESS (A, B, Cin, alu_op)
	Variable Resulttmp : std_logic_vector (15 downto 0);
	variable CoutTmp : std_logic;
     BEGIN   
	CASE  alu_op  IS
			WHEN op_A =>  Zout<= A;  Cout <= '0'; --op_A
			WHEN op_B =>  Zout<= B;  Cout <= '0'; --op_B
			WHEN op_notA =>  Zout<= not A;  Cout <= '0'; --op_notA
			WHEN op_notB =>  Zout<= not B;  Cout <= '0'; --op_notB
			WHEN op_AxorB =>  Zout<= A xor B;  Cout <= '0'; --op_AxorB
			WHEN op_AorB =>  Zout<= A or B;  Cout <= '0'; --op_AorB
			WHEN op_AandB =>  Zout<= A and B;  Cout <= '0'; --op_AandB
			WHEN op_AnandB =>  Zout<= A nand B;  Cout <= '0'; --op_AnandB
			WHEN op_AxnorB =>  Zout<= A xnor B;  Cout <= '0'; --op_AxnorB
			WHEN op_0 =>  Zout<= "0000000000000000";  Cout <= '0'; --op_0
			WHEN op_1 =>  Zout<= "1111111111111111";  Cout <= '0'; --op_1
			WHEN op_incA =>  binadd(A,"0000000000000000",'1',resulttmp, CoutTmp); Zout <= resulttmp; Cout <= CoutTmp; --op_incA
			WHEN op_incB =>  binadd(B,"0000000000000000",'1',resulttmp, CoutTmp); Zout <= resulttmp; Cout <= CoutTmp; --op_incB
			WHEN op_decA =>  binsub(A,"0000000000000000",'1',resulttmp, CoutTmp); Zout <= resulttmp; Cout <= CoutTmp; --op_decA
			WHEN op_decB =>  binsub(B,"0000000000000000",'1',resulttmp, CoutTmp); Zout <= resulttmp; Cout <= CoutTmp; --op_decB
			WHEN op_negA =>  neg(A, resulttmp, CoutTmp); Zout <= resulttmp; Cout <= CoutTmp; --op_negA
			WHEN op_negB =>  neg(B, resulttmp, CoutTmp); Zout <= resulttmp; Cout <= CoutTmp; --op_negB
			WHEN op_AplusB =>  binadd(A,B,Cin,resulttmp, CoutTmp); Zout <= resulttmp; Cout <= CoutTmp; --op_AplusB
			WHEN op_AplusBwC =>  binadd(A,B,Cin,resulttmp, CoutTmp); Zout <= resulttmp; Cout <= CoutTmp; --op_AplusBwC 
			WHEN op_AminB =>  binsub(A,B,Cin,resulttmp, CoutTmp); Zout <= resulttmp; Cout <= CoutTmp; --op_AminB
			WHEN op_BminA =>  binsub(B,A,Cin,resulttmp, CoutTmp); Zout <= resulttmp; Cout <= CoutTmp; --op_BminA
			WHEN OTHERS         =>  NULL;
	END CASE;
	--if Zout(15)/='1' or Zout(15)/='0' then n <= '0';
	--else N <= Zout(15);
	--end if;
	N <= Zout(15);
	if zout = "0000000000000000" then z <= '1';
	else z <= '0';
	end if;
  END PROCESS;
END ALU16std_logicpwn;

LIBRARY  IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE work.step8_package.all;
ENTITY DataPAthCoastn IS
  PORT (ABUS,BBUS : INOUT std_logic_vector (15 downto 0) := "ZZZZZZZZZZZZZZZZ";
		Aregload,Bregload,Aregdrive,Bregdrive,Cin : IN std_logic;
		A_ALUload,B_ALUload,A_ALUdrive,B_ALUdrive  : IN std_logic;
		C,N,Z : OUT std_logic;
		alu_op : IN operations;
		AregNo,BregNo : IN integer := 0);
END DataPAthCoastn;
-------------------------------------------------------------------------------
--  Enter your Architecture for a the datapath here
-------------------------------------------------------------------------------
ARCHITECTURE datpatharch OF DataPAthCoastn IS
	TYPE   regs_type IS array (0 to 15) of std_logic_vector (15 downto 0);
	signal a,b,zout   : std_logic_vector(15 downto 0) := "ZZZZZZZZZZZZZZZZ";
		  COMPONENT alu_16std_logic
		PORT ( alu_op : IN operations;
                  a,b   : IN std_logic_vector(15 downto 0);
                  Cin   : IN std_logic;
                  Zout  : INOUT std_logic_vector(15 downto 0);
                  Cout,n,z : OUT std_logic);
		END COMPONENT;
		FOR ALL : alu_16std_logic USE ENTITY WORK.alu_16std_logic(ALU16std_logicpwn); 
BEGIN
alu16good : alu_16std_logic PORT MAP(alu_op,A,B,Cin,Zout,C,n,z);	
	PROCESS (ABUS,BBUS,Aregload,Bregload,Aregdrive,Bregdrive,AregNo,BregNo,A_ALUload,B_ALUload,A_ALUdrive,B_ALUdrive)
		VARIABLE RegSet  : regs_type := ("ZZZZZZZZZZZZZZZZ","ZZZZZZZZZZZZZZZZ", -- set initial state to highz
		"ZZZZZZZZZZZZZZZZ","ZZZZZZZZZZZZZZZZ","ZZZZZZZZZZZZZZZZ","ZZZZZZZZZZZZZZZZ",
		"ZZZZZZZZZZZZZZZZ","ZZZZZZZZZZZZZZZZ","ZZZZZZZZZZZZZZZZ","ZZZZZZZZZZZZZZZZ",
		"ZZZZZZZZZZZZZZZZ","ZZZZZZZZZZZZZZZZ","ZZZZZZZZZZZZZZZZ","ZZZZZZZZZZZZZZZZ",
		"ZZZZZZZZZZZZZZZZ","ZZZZZZZZZZZZZZZZ");

    BEGIN   	
		IF (Aregload='1' AND Aregload'event) THEN  -- load A on rising edge of Aregload
			RegSet(AregNo):=ABUS;
		END IF;
		IF (A_ALUload='1' AND A_ALUload'event) THEN  -- load A on rising edge of A_ALUload
			if a="ZZZZZZZZZZZZZZZZ" then a <= "0000000000000000";
			else a<=ABUS;
			END IF;
		END IF;
		IF (Bregload='1' AND Bregload'event) THEN  -- load B on rising edge of Bregload
			RegSet(BregNo):=BBUS;
		END IF;
		IF (B_ALUload='1' AND B_ALUload'event) THEN  -- load B on rising edge of B_ALUload
			if b="ZZZZZZZZZZZZZZZZ" then b <= "0000000000000000";
			else b<=BBUS;
			END IF;
		END IF;
		IF (Aregdrive='0') THEN  -- drive reg(n) value to A bus when Aregdrive = low
			ABUS<=RegSet(AregNo);
		END IF;
		IF (A_ALUdrive='0') THEN  -- drive reg(n) value to A bus when A_ALUdrive = low
			ABUS<=Zout;
		END IF;
		IF (Bregdrive='0') THEN  -- drive reg(n) value to B bus when Bregdrive = low
			BBUS<=RegSet(BregNo);
		END IF;
		IF (B_ALUdrive='0') THEN  -- drive reg(n) value to B bus when B_ALUdrive = low
			BBUS<=Zout;
		END IF;
		IF (Aregdrive='1' AND Aregdrive'event) THEN  -- load hiz to A bus on rising edge of Aregdrive
			ABUS<="ZZZZZZZZZZZZZZZZ";
		END IF;
		IF (A_ALUdrive='1' AND A_ALUdrive'event) THEN  -- load hiz to A bus on rising edge of A_ALUdrive
			ABUS<="ZZZZZZZZZZZZZZZZ";
		END IF;
		IF (Bregdrive='1' AND Bregdrive'event) THEN  -- load hiz to B bus on rising edge of Bregdrive
			BBUS<="ZZZZZZZZZZZZZZZZ";
		END IF;
		IF (B_ALUdrive='1' AND B_ALUdrive'event) THEN  -- load hiz to B bus on rising edge of B_ALUdrive
			BBUS<="ZZZZZZZZZZZZZZZZ";
		END IF;
	END PROCESS;
END datpatharch;

[ewmayer]

Originally Posted by science_man_88

you are already on the 7th line by the time something even remotely close sounding comes up. I was going to go over potential structure we could use but what ever.

My bad - I mixed up the refrain with the opening ... perhaps because imagining a bunch of white people loudly singing about Canada as their 'native land' induces cognitive dissonance.

Back to the original off-topic ... suggest you ask user mancoast for timings of his spiffy 'sm88-mul' code on (say) a 70-mbit input, and then see if you double the speed via some of the optimizations you mentioned.

[chalsall]

Originally Posted by ewmayer

My bad - I mixed up the refrain with the opening ... perhaps because imagining a bunch of white people loudly singing about Canada as their 'native land' induces cognitive dissonance.

Hey!

At least Canadians never imported slaves.

[petrw1]

Originally Posted by ewmayer

I suppose a national anthem whose wording opens with "Oh, Canada! We stand on cars and freeze..." is rather a big tip-off, innit?

Good one ... I resemble that remark.

[ewmayer]

Originally Posted by chalsall

Hey!

At least Canadians never imported slaves.

You sure about that? (Clearly at a drastically lesser level than their southern neighbo(u)r, obviously.)

OTOH they did name one of their notable lakes in homage to the practice (in this case, as practiced by a native tribe). Petrw1, that's kinda/sorta in your neck of the, um, plains, yes? (Just a short 1000-mile - sorry, 1600-km - drive NW and you're there.)