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#188 |
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P90 years forever!
Aug 2002
Yeehaw, FL
19·397 Posts |
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#189 |
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∂2ω=0
Sep 2002
República de California
19·613 Posts |
Aside from the FMA3 support, you mean? ;)
[I know, strictly speaking these are separate additions to the ISA, but since they appeared together in the same chip release I usually think of both the the 256-bit-wide SIMD-ints and the FMA3 as "AVX2".] Of course for AMD, FMA support is "SSE5", and it's FMA4, not FMA3. Clear as mud. Last fiddled with by ewmayer on 2013-07-17 at 00:30 |
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#190 |
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P90 years forever!
Aug 2002
Yeehaw, FL
19×397 Posts |
and there are separate CPUID flags for FMA and AVX2. Yes, clear as mud.
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#191 | |
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Romulan Interpreter
Jun 2011
Thailand
26·151 Posts |
Quote:
Wouldn't be much simpler to disconnect your fans?
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#192 |
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May 2013
East. Always East.
110101111112 Posts |
But shouldn't there be a massive slowdown on four workers if the memory is bottlenecked even at two workers?
Like I said in my previous post, my test had 11, 11, 11, and then finally 14 milliseconds once the fourth worker was added. In George's test, they are getting progressively longer, yes, but the bottleneck begins right at two workers. |
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#193 |
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"GIMFS"
Sep 2002
Oeiras, Portugal
5C216 Posts |
@George,
Was the system stable enough @4.2 GHz to be considered fit for day-to-day crunching? (day-to-day meaning 24/7 LLtesting) And did you take any power consumption measurement at that speed? Thx |
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#194 | |
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P90 years forever!
Aug 2002
Yeehaw, FL
19×397 Posts |
Quote:
I have not taken any power consumption measurements. |
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#195 | |
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P90 years forever!
Aug 2002
Yeehaw, FL
19×397 Posts |
Quote:
What if each iteration did no FPU operations? That is, all it did was read and write memory. One worker would take about 5ms. Now when you start the second worker, *every* time it wants to read or write from memory it must wait. Each worker will now take 10ms. Third worker 15ms. Fourth worker 20ms. Prime95 isn't as bad as this what if case. Instead of worker two waiting *every* time it accesses memory, it only has to wait say 5 percent of the time -- a partial slowdown. The key here is the faster the CPU portion of prime95, the more penalty you'll see as you add another worker. Last fiddled with by Prime95 on 2013-07-17 at 14:25 |
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#196 |
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Apr 2010
Over the rainbow
2×1,303 Posts |
i7-4960 tested
http://www.tomshardware.com/reviews/...rk,3557-5.html |
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#197 |
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P90 years forever!
Aug 2002
Yeehaw, FL
754310 Posts |
I created a torture test that uses really small FFTs that fit in the L1 data cache. Alas, it runs cooler than the FFTs that fit in the L2 data cache.
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#198 |
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∂2ω=0
Sep 2002
República de California
19×613 Posts |
L2 caches are so much larger that the overall die heating is probably more when one has all levels of the on-chip memory hierarchy busy.
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