Launch of the AMD FX 8 Core processor - Page 2

fivemack · 2011-10-12, 12:40

The dual-Xeon has six memory controllers and the 1100T has two; msieve in my experience scales with the number of memory controllers. I haven't made measurements of the difference between -t4 and -t6 on a six-core Intel or AMD machine, but other people on this forum I think have.

Of course the dual-Xeon machine costs at least four times as much as the 1100T machine.

I would wait a couple of months and see how well Sandy Bridge E does, since it has four memory controllers at a not-unreasonable price.

Batalov · 2011-10-12, 18:04

Quote:

Originally Posted by em99010pepe

For msieve use in LA phase do you recommend one AMD 1100T with 16 GB or one dual Intel® Xeon™ X5650 SixCore 2.26GHz 12M 6,4 QPI 12 MB with 4x Dimm 8GB 1333MHz DDR3 ECC Reg w/Parity CL9 DIMM? Does msieve scale well with increase of number of cores? Sorry for the question but I have not experience running msieve on a CPU with more than 4 cores.

Thanks in advance,

Carlos

Alas, for linear algebra, 4 to 6-core transition (940 to 1055T) already left me disappointed, scaling was not too good - it was existent but significantly levelled. Arguably part of the reason is mentioned by Tom (especially with the DDR2 board and memory that I kept from 940). Dual Xeon did much better (but I only had a short window to test and not own it); it was a $10K+ system though, not far to compare.

1055T was not a total waste, because while running LA with -t 4 one may run some two extra processes on the backburner. (I'll build two computers for kids out of all these parts a bit later.)

I am no longer too excited about this release; just revived the thread. Now, after reviews, the power consumption seems to be quite a nail in its OC potential's coffin. (300W+ with light OC? gaaah!)

nucleon · 2011-10-12, 21:43

Quote:

Originally Posted by fivemack

I would wait a couple of months and see how well Sandy Bridge E does, since it has four memory controllers at a not-unreasonable price.

SNB-E first looks:

http://www.tomshardware.com/reviews/...ance,3026.html

6cores, 50GB/sec mem speed, drool.

It is a _demon_ with memory performance. This thing is a P-1 specialist. I found with my pseudo-scientific testing, that memory speed was important for P-1 to a point.

-- Craig

nucleon · 2011-10-12, 21:47

Bulldozer with it's 1FP per 2 int cores, will be interesting to see what's the optimal prime95 run. I know on the '8' core cpu, it won't be 8x LL. Maybe 4x LL and 4x TF perhaps? Depends on memory bandwidth, ala core2 quads.

-- Craig

Dubslow · 2011-10-12, 21:48

As for the Bulldozer shared FPU thing, the first graph here shows that it actually manages to keep apiece the 2600k. Considering it's other failings though, I'd just go with a 2600k, 2500k, or better yet, save up for Ivy Bridge. That's supposed to be a 30% performance gain over SB at the same power. I want to see that!

Christenson · 2011-10-12, 23:40

What if we set the first integer core to feed factor candidates to mfaktc, and the second one and the FPU to do LL tests? That sound like a good mix?

Dubslow · 2011-10-13, 00:09

Good luck coding that

Would the scheduler be smart enough to lock down the FPU to the LL?

Christenson · 2011-10-13, 01:47

I think it would be a matter of auditing mfaktc on the CPU side and making sure it made relatively few floating point calls...or possibly none at all, saving the context switches...the rest is done in task manager when we tell it how we want to use the cores.

I do such things in motor control codes, and mfaktc isn't all that complicated.

nucleon · 2011-10-13, 09:00

Quote:

Originally Posted by Christenson

What if we set the first integer core to feed factor candidates to mfaktc, and the second one and the FPU to do LL tests? That sound like a good mix?

Definitely. Sounds like a plan. The hard part would be to work out the core numbering. Say the cores go like this: fp core split over core0 and core1, then core2 and core 3 etc.... So your work distribution would be:

Core0: Prime95 LL testing
Core1: mfaktc instance0
Core2: Prime95 LL testing
Core3: mfaktc instance1
Core4: Prime95 LL testing
Core5: mfaktc instance2
etc...

That is easily mapped under windows.

That would suit up to say 2x GTX560Ti cards. That would suit 1x GTX580 easily. Depends on clock speed of CPU and available IO. You might get away with 2x GTX570s, YMMV. I had a 2600k clocked to 4.5GHz and that was almost enough to drive 2x GTX580s. It can drive a GTX580 and GTX460 though.

-- Craig
*By drive I mean get at least 95% GPU utilization with mfaktc.

Dubslow · 2011-10-13, 19:02

Even though this would work fine, it still seems you'd get better value/throughput by waiting for Ivy Bridge

nucleon · 2011-10-13, 21:20

Quote:

Originally Posted by Dubslow

Even though this would work fine, it still seems you'd get better value/throughput by waiting for Ivy Bridge

:)

Ivy Bridge will still only be 4x cores, hopefully they'll increase the production clock rate a bit.

I'm keen on Sandy Bridge-E CPUs. Granted a bit more on the pricey, by oodles of memory bandwidth will make them a P-1 beast. And they'll be 6 cores.

-- Craig

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2011-10-12, 12:40	#12
fivemack (loop (#_fork)) Feb 2006 Cambridge, England 2·7·461 Posts	The dual-Xeon has six memory controllers and the 1100T has two; msieve in my experience scales with the number of memory controllers. I haven't made measurements of the difference between -t4 and -t6 on a six-core Intel or AMD machine, but other people on this forum I think have. Of course the dual-Xeon machine costs at least four times as much as the 1100T machine. I would wait a couple of months and see how well Sandy Bridge E does, since it has four memory controllers at a not-unreasonable price.

2011-10-12, 21:47	#15
nucleon Mar 2003 Melbourne 5×103 Posts	Bulldozer with it's 1FP per 2 int cores, will be interesting to see what's the optimal prime95 run. I know on the '8' core cpu, it won't be 8x LL. Maybe 4x LL and 4x TF perhaps? Depends on memory bandwidth, ala core2 quads. -- Craig

2011-10-12, 21:48	#16
Dubslow Basketry That Evening! "Bunslow the Bold" Jun 2011 40<A<43 -89<O<-88 3×29×83 Posts	As for the Bulldozer shared FPU thing, the first graph here shows that it actually manages to keep apiece the 2600k. Considering it's other failings though, I'd just go with a 2600k, 2500k, or better yet, save up for Ivy Bridge. That's supposed to be a 30% performance gain over SB at the same power. I want to see that!

2011-10-12, 23:40	#17
Christenson Dec 2010 Monticello 3403₈ Posts	What if we set the first integer core to feed factor candidates to mfaktc, and the second one and the FPU to do LL tests? That sound like a good mix?

2011-10-13, 00:09	#18
Dubslow Basketry That Evening! "Bunslow the Bold" Jun 2011 40<A<43 -89<O<-88 3×29×83 Posts	Good luck coding that Would the scheduler be smart enough to lock down the FPU to the LL?

2011-10-13, 01:47	#19
Christenson Dec 2010 Monticello 3403₈ Posts	I think it would be a matter of auditing mfaktc on the CPU side and making sure it made relatively few floating point calls...or possibly none at all, saving the context switches...the rest is done in task manager when we tell it how we want to use the cores. I do such things in motor control codes, and mfaktc isn't all that complicated.

2011-10-13, 19:02	#21
Dubslow Basketry That Evening! "Bunslow the Bold" Jun 2011 40<A<43 -89<O<-88 3×29×83 Posts	Even though this would work fine, it still seems you'd get better value/throughput by waiting for Ivy Bridge