Power 2 - Page 5

JohnFullspeed · 2011-07-10, 16:13

Intel documentation says 8 cycles fot BSL BSR

BFR a,R0 8 <= CISC RISC => 1
Bsl a,R1 8 1
Sub R1,R1,R3 1 1
RTN R3 = 17 =3

MOVA,R 1 1
MOV A,R1 1 1
Sub R1,1,R3 1 1
AND R1,R2,R3 1 1
RTN R3 = 4 =4

Christenson · 2011-07-10, 20:13

Having multiple methods and testing them at run-time also lets you run on non-intel CPUs (including your favorite RISC, and my AMD Phenom II x6). Also, on an issue like that, my past personal experience with Intel documentation carelessness (as well as LavaLamp's note from the chess programmers) makes me very concerned about its accuracy. An error like that simply won't make the news.

2011-07-10, 16:13	#45
JohnFullspeed May 2011 France 241₈ Posts	intel Intel documentation says 8 cycles fot BSL BSR BFR a,R0 8 <= CISC RISC => 1 Bsl a,R1 8 1 Sub R1,R1,R3 1 1 RTN R3 = 17 =3 MOVA,R 1 1 MOV A,R1 1 1 Sub R1,1,R3 1 1 AND R1,R2,R3 1 1 RTN R3 = 4 =4

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2011-07-10, 20:13	#46
Christenson Dec 2010 Monticello 5×359 Posts	Having multiple methods and testing them at run-time also lets you run on non-intel CPUs (including your favorite RISC, and my AMD Phenom II x6). Also, on an issue like that, my past personal experience with Intel documentation carelessness (as well as LavaLamp's note from the chess programmers) makes me very concerned about its accuracy. An error like that simply won't make the news.