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#12 | |
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I quite division it
"Chris"
Feb 2005
England
207710 Posts |
Quote:
Tony's guess of 2023 looked too far ahead so I went about half way. I was also figuring on a couple of hardware breakthroughs and everyone having 16 or 32 cores. It's all my other posts that are pure plagiarism. edit: I was also thinking that there might be a reward for the first 100m digit prime, so people would be searching artificially high. Last fiddled with by Flatlander on 2008-09-14 at 15:14 |
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#13 |
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Feb 2004
France
22×229 Posts |
The main problem with many cores is the difficulty/cost to have a good hardware and software scalability !!
HW scalability is VERY expensive now. FFT scalability is difficult. Preliminary results (to be confirmed) are showing that, on a 8 cores, Mlucas is running 5.4 times faster than with only 1, though Prime95 has a 3.3 factor only. It would be worst with 16 or 32 cores. IBM/Bull Power machines are VERY scalable ! But a 64xPower6 machine costs more than 1MEuros... Tony |
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#14 | |
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"Lucan"
Dec 2006
England
2·3·13·83 Posts |
Quote:
a multiplying by ten in the power needed to keep up: iterations x numbers to test x time per iteration. People tried leaping to 10M digits a long time ago without success. David Last fiddled with by davieddy on 2008-09-14 at 15:51 |
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#15 |
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Undefined
"The unspeakable one"
Jun 2006
My evil lair
11000001101002 Posts |
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#16 | |
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I quite division it
"Chris"
Feb 2005
England
31·67 Posts |
Quote:
)edit (Will I never learn?): How big would an on-die cache have to be to hold a 100m digit test? Last fiddled with by Flatlander on 2008-09-14 at 16:36 |
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#17 | |
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Feb 2004
France
22·229 Posts |
Quote:
T. |
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#18 | |
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Dec 2003
Hopefully Near M48
2·3·293 Posts |
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#19 | |
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Bemusing Prompter
"Danny"
Dec 2002
California
45268 Posts |
Quote:
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#20 |
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Just call me Henry
"David"
Sep 2007
Cambridge (GMT/BST)
23×3×5×72 Posts |
25.6 is a new version of Prime95
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#21 |
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Apr 2008
Regensburg..^~^..PlzeĆ
5·17 Posts |
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#22 | |
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(loop (#_fork))
Feb 2006
Cambridge, England
11001000100112 Posts |
Quote:
(to calibrate, current ultra-high-end is Dunnington, high-end infinitely-rich-gamer is QX9772, normal-user is Q6600) Tulsa ('Xeon 7100 series') has a 16MB L3 cache made with 0.624um^2 cells in 65nm; the Itanium 9100 has a 24MB L3 cache made with 1um^2 cells in 90nm but that's still only about 190mm^2. So it's probably unrealistic to expect more than 100mm^2 of L3 cache on any remotely affordable processor. |
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