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#375 | ||
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∂2ω=0
Sep 2002
República de California
19×613 Posts |
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- Finish translation of MSVC-style inline ASM code to GCC syntax - Add Primenet networking support - Lots of profiling and tuning of the multithreading - Perhaps try some 64-bit-OS-specific optimizations - Maybe bang together a basic Qt-based GUI ...and this in the plentiful [that's a joke, BTW] time left to me by my for-pay job. That means a lot of not-having-a-life-outside-of-work, but with the proverbial finish line in sight, gotta gut it out at least through the release and initial wave of widescale testing. Quote:
Rob, I'm just curious - has Sun organized any small PR-related blurbs around this? With all the bad-news-on-so-many-other-fronts and questions about their business strategy having hammered their share price this year, you'd think they'd be hungry for some good PR about their shiny new Sparc-based server hardware. I have no special interest in the company [except that being a speed whore I do enjoy access to the fancy hardware and latest compilers] and own no stock, but I remember Sun in its Sparc 1 & 2 heyday and dislike the thought of one of the last remaining RISC-chip vendors [especially now that they seem to have gotten their chip-design act back together again after the doldrums of the Sparc 3 thru V] getting out of the CPU business. Competition is good, and it seems every year Intel has less of it. |
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#376 |
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Dec 2003
Hopefully Near M48
6DE16 Posts |
Maybe I'm just really stupid; but aren't there 4 verifiers?
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#377 |
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Apr 2006
Down Under
8910 Posts |
I think it's a little misleading as there is a collective of Tom Duell & I (Rob Giltrap) running one test using Ernst's Mlucas 3.0 pre-release code. Actually we're now running two copies in parallel on SPARC64 VI & SPARC64 VII.
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#378 |
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Apprentice Crank
Mar 2006
2·227 Posts |
I'm guessing that the large number of verifications going on indicates that this is a 10M + digit prime.
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#379 |
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∂2ω=0
Sep 2002
República de California
2D7F16 Posts |
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#380 | |
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Einyen
Dec 2003
Denmark
2×1,579 Posts |
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Comparing to x86 hardware at 4096K FFT (75M exponent) in Prime95: Core2Duo (Conroe) E6750 2.66 Ghz: 55.4 ms/iteration (both cores on it) Core2Quad (Yorksfield) Q9450 2.66 Ghz: 43.4 ms/iteration (all 4 cores on it) Last fiddled with by ATH on 2008-09-05 at 20:49 |
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#381 | |||
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Apprentice Crank
Mar 2006
2·227 Posts |
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Therefore, 950,400 seconds * 45 iterations/sec = 42,768,000, which is well into the 10M+ digit range. So, what is the actual exponent? For that, we have to look at a guess posted earlier and it's response: Quote:
Quote:
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#382 |
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"Richard B. Woods"
Aug 2002
Wisconsin USA
1E0C16 Posts |
(* mumble *) inflation factor (* mumble *) ...
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#383 | ||
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Apr 2006
Down Under
89 Posts |
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Niagara2 at 64 threads is an incredibly impressive "system on a chip" which just eats workload with linear performance for horizontal applications (truly unique). The forthcoming Rock again is a radical departure from the norm which really fits well with the Sun culture of civil disobedience. ![]() Then the SPARC64 VI/VII line is just a lovely dose of BRUTE FORCE. Nice balance of clock speed vs cache size vs SMP scalability vs large I/O. I have a customer that dubbed the M-series systems as Hoovers based on their ability to suck and blow I/O from and to the fastest of SANs. Those working in the enterprise space know it's all about I/O these days. Finally, Sun's re-embrace of x64 gives a whole arsenal of AMD & Intel systems to play with and with the likes of Intel's David Stewart and team providing some OpenSolaris love, Sun is well and truly back at the forefront of systems technology. Last fiddled with by rgiltrap on 2008-09-05 at 22:45 |
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#384 | ||
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Dec 2003
Hopefully Near M48
33368 Posts |
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I see. So Ernst isn't personally doing a verification run. Last fiddled with by jinydu on 2008-09-06 at 00:54 |
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#385 |
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"Lucan"
Dec 2006
England
2×3×13×83 Posts |
Ernst,
At St Paul's School I taught a potential whizz kid named Tony Duell. No relation by any chance? David |
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