Ryzen "3D V-Cache", 96MiB L3 per chiplet

[M344587487]

Originally Posted by mackerel

...
Hot info from Ian Cutress of Ananadtech: "Confirmed with AMD that V-Cache will be coming to Ryzen Zen 3 products, with production at end of year."
https://twitter.com/IanCutress/statu...66139769602058

This is pure guess on my part, extra cache Zen3 parts may be used to push back the Zen4 release and smooth out supply issues transitioning to 5nm. Probably also used as a stall tactic to wait and see if and how far intel fails to deliver with their next gen. I wonder if 7nm SRAM can and will be paired with 5nm chiplets in the future.

[mackerel]

Zen 4 being later than sooner is an often discussed possibility, but it wasn't so much due to 5nm as DDR5 as the given reason. If Intel go DDR5 first, they'll take the early adopter hit on pricing while they gear up the market, then AMD can stroll along and pick up once it is more established. We see that kind of move a lot from AMD, don't know how much is due to choice or necessity though.

[nordi]

Originally Posted by mackerel

I'm wondering where the 2 TB/s claim comes from. Can 8 cores move data in/out of that cache at that speed? Or it is a theoretical maximum based on stacking? I don't have numbers for Zen 3 currently, what does that do as currently sold? I did a quick Aida64 on my 8 core Cezanne and that's only 100GB/s copy in L3.

This graphic from Anandtech's Zen3 deep dive shows "32B / cycle" as L3 bandwith per core. At 4Ghz, that's 128GB/s, which is in line with your 100. For 16 cores, the total bandwidth is 16*128GB/s = 2TB/s. Maybe that's where the number comes from. Anyway, the cores themselves could use up the bandwidth already, so the question is if the L3 cache can deliver it.

For anyone that wants to see Lisa Su's original announcent, it's here. Not sure if all the articles that were written are based on additional sources, or just those 5 minutes of video.

[M344587487]

A bigger deal for general use might be iGPU's, currently they are what a typical person will encounter memory bandwidth limitations with if anything and the improvement could be sizeable. A unified cache for CPU and GPU is probably too complicated (or is it? If they want to resume pursuing HSA it may be a natural progression), but who's to say that the SRAM can't be attached to the iGPU as infinity cache instead of the CPU as v-cache? Better yet have a bios boot option to set the 64MiB SRAM stack as either V-cache or infinity cache, given how modular AMD has been lately I would bet that the two technologies largely differ only in the controller used.

Currently you can use a Ryzen APU for "good enough at 720P, mostly" gaming. It would be nice if the baseline can jump to "good enough at 1080P, mostly".

[JWNoctis]

More news coming out: 64-Core Zen 3 EPYC with 96MiB * 8 L3 cache, 10% overhead to overall latency, vast performance improvement projected for enterprise workload.

Supposedly they also have preview instances on Azure now.

[JWNoctis]

So it's coming out soon. $100 listed-price premium for lower base and boost clock, apparently no overclocking, and 64MiB more of L3 cache. Enough L3 for wavefront PRP for the foreseeable future, but may well hit L3 ringbus limit.

Workloads exceeding L3 size may well end up slower due no IF/MMU overclocking.

Curious.

https://www.techpowerup.com/292256/a...esign-at-isscc
https://arstechnica.com/gadgets/2022...il-20-for-449/

[JWNoctis]

Correction: They do support IF/MMU overclocking after all. Enticing.

[M344587487]

The server version reviews are out, some of the HPC uplift looks very tasty: https://www.phoronix.com/scan.php?pa...yc-7773x-linux

[Mark Rose]

As expected, the 5800X3D does better at large FFTs: https://www.mersenneforum.org/showpo...&postcount=872

[joblack]

Anyone tried a Ryzen 5800X3D with Prime95 for large (100M) Mersenne prime checks? How is it doing?