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#1 |
May 2008
3·5·73 Posts |
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In stage1_sieve.c:
Code:
/* structures for storing arithmetic progressions. Rational leading coeffs of NFS polynomials are assumed to be the product of two groups of factors p, each of size at most 32 bits (32 bits is enough for 512-bit factorizations), and candidates must satisfy a condition modulo p^2 */ #define MAX_P ((uint64)(-1)) But, for degree==4, max p is still 32 bits. Code:
if (degree == 4) { CUDA_TRY(cuModuleGetGlobal(&L.gpu_p_array, NULL, gpu_module64, "pbatch")) done = sieve_lattice_gpu_deg4_64(obj, &L, &sieve_small, &sieve_large, (uint32)small_p_min, (uint32)small_p_max, (uint32)large_p_min, (uint32)large_p_max, gpu_info, gpu_kernel64); } The attached patch does a simple fix for this. |
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#2 |
May 2008
3·5·73 Posts |
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Forgot to mention, this is about msieve-GPU only.
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#3 |
May 2008
3×5×73 Posts |
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Maybe it would be better to instead have different MAX_P defined for the different degrees. (uint32)(-1) for degree==4 and (uint64)(-1) for larger degrees.
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#4 |
May 2008
3·5·73 Posts |
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I like this patch better than the earlier one. See attached.
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#5 |
Tribal Bullet
Oct 2004
353710 Posts |
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