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Old 2011-07-01, 18:06   #34
clarke
 
Feb 2009

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Yep, for 2.700MHz processor I have similar id
AMD Athlon(tm) 7750 Dual-Core Processor
CPU speed: 8736.40 MHz, 2 cores
CPU features: Prefetch, 3DNow!, MMX, SSE, SSE2
L1 cache size: 64 KB
L2 cache size: 512 KB, L3 cache size: 2 MB
L1 cache line size: 64 bytes
L2 cache line size: 64 bytes
L1 TLBS: 48
L2 TLBS: 512
Prime95 32-bit version 26.6, RdtscTiming=1
In 26.4 slighly overcklocked CPU was detected as
AMD Athlon(tm) 7750 Dual-Core Processor
CPU speed: 2999.84 MHz, 2 cores
CPU features: RDTSC, CMOV, Prefetch, 3DNow!, MMX, SSE, SSE2
L1 cache size: 64 KB
L2 cache size: 512 KB, L3 cache size: 2 MB
L1 cache line size: 64 bytes
L2 cache line size: 64 bytes
L1 TLBS: 48
L2 TLBS: 512
Prime95 32-bit version 26.4, RdtscTiming=1

Last fiddled with by clarke on 2011-07-01 at 18:06
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Old 2011-07-03, 20:02   #35
Christenson
 
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Monticello

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This probably isn't high on the priority list, but.....
Bug in P95, 26.6 source, at top of commonb.c: Various security functions are declared to be integer zero instead of long zero. This leads to warnings for those of us doing alternate builds of the code, which i really don't want when building mfaktc unless absolutely necessary.

For really good form, security.h itself does these #defines.

I was surprised at the "multiple include" model of building things, I assume this simplifies the writing of makefiles, which at least some organisations have found is completely daft when trying to scale it up.

Eric Christenson
Code:
#include "security.h"
#ifndef SEC1
#define SEC1(p)            0UL
#define SEC2(p,hi,lo,u,e)    0UL
#define SEC3(p)            0UL
#define SEC4(p)            0  //not sure this doesn't also need a UL, but didn't track it down and wasn't warned.
#define SEC5(p,b1,b2)        0UL
#endif
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Old 2011-07-08, 17:08   #36
kladner
 
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"Kieren"
Jul 2011
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Default Extreme CPU speed report

I am showing a similar impossible speed result on a Phenom II x6 1090T. It is actually running stock at 3.2GHz. (Twould be nice to have that 9.4+GHz, but I'm fresh out of liquid nitrogen.)
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Old 2011-07-23, 01:02   #37
liqi
 
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Quote:
Originally Posted by kladner View Post
I am showing a similar impossible speed result on a Phenom II x6 1090T. It is actually running stock at 3.2GHz. (Twould be nice to have that 9.4+GHz, but I'm fresh out of liquid nitrogen.)
seems only AMD cpus on version 26.6 have this bug.
while Intel`s do not have.
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Old 2011-08-16, 03:07   #38
bjornstar
 

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Default Not Intel and not AMD

In version 26.6 it now says "Optimizing for CPU architecture: Not Intel and not AMD, L2 cache size: 4 KB"

There is a non-vendor specific way of detecting cache sizes using CPUID that would be preferable. Prime95 v26.6 is now optimizing for 4KB of cache on VIA CPUs when there could be up to 4MB of cache.

Is there someone I can talk to about correctly detecting cache sizes across all x86 vendors?
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Old 2011-08-17, 10:58   #39
Nelson
 
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Regensburg..^~^..Plzeň

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Quote:
Originally Posted by Christenson View Post
Hey, if you are fixing zero-based core versus 1-based core reporting, how's about having the assignments page on the server do 1-based core reporting so I don't have to translate?

Thanks
The affinity string (01234...XYZ) doesn’t seem to work properly. Should it be (1234...XYZ instead)? Otherwise the affinity string is non functional and I had to stay with v26.5 for it to group my workers correctly on a Core2Quad. It has a sizable impact on iteration times (59ms instead of 49ms) or (36ms instead of 29ms).

I’m Using SuseLinux v11.4 and have an ongoing problem with mprime communicating with the server before the network is fully setup. Could the startup delay give enough time for the network to stabilize before trying to communicate? Internet connection is via external router and I am already browsing the internet on other machines on the network when this happens.

nelson
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Old 2011-08-18, 02:59   #40
kgfu
 

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Unhappy Compiling prime95

I try to compiler the prime95 source code with virtual studio 2008, with libcurl 7.18.0-win32-msvc. I have modify the libcurl.lib and libcurl.dll directory on the project, but I still get a error that can't open the prime95.exe...help me!!
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Old 2011-08-18, 09:26   #41
henryzz
Just call me Henry
 
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Sep 2007
Cambridge (GMT/BST)

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Quote:
Originally Posted by bjornstar View Post
In version 26.6 it now says "Optimizing for CPU architecture: Not Intel and not AMD, L2 cache size: 4 KB"

There is a non-vendor specific way of detecting cache sizes using CPUID that would be preferable. Prime95 v26.6 is now optimizing for 4KB of cache on VIA CPUs when there could be up to 4MB of cache.

Is there someone I can talk to about correctly detecting cache sizes across all x86 vendors?
Try looking at undoc.txt.
Quote:
Originally Posted by Prime95 25.9 undoc.txt
The program also supports different code paths for LL testing on a Pentium 4
based on the size of the L2 cache. You can explicitly specify the L2 cache
size although this shouldn't be necessary since the program uses the CPUID
instruction to determine the L2 cache size. In local.txt enter:
CpuL2CacheSize=128 or 256 or 512
CpuL2CacheLineSize=32 or 64 or 128
CpuL2SetAssociative=4 or 8
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Old 2011-08-28, 15:59   #42
moebius
 
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once more the same...

[Sun Aug 28 17:33:33 2011]
Compare your results to other computers at http://www.mersenne.org/report_benchmarks
AMD Phenom(tm) II X4 955 Processor
CPU speed: 9183.92 MHz, 4 cores
CPU features: Prefetch, 3DNow!, MMX, SSE, SSE2
L1 cache size: 64 KB
L2 cache size: 512 KB, L3 cache size: 6 MB
L1 cache line size: 64 bytes
L2 cache line size: 64 bytes
L1 TLBS: 48
L2 TLBS: 512
Prime95 64-bit version 26.6, RdtscTiming=1

Last fiddled with by moebius on 2011-08-28 at 16:01
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Old 2011-08-29, 12:06   #43
Prime95
P90 years forever!
 
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Yeehaw, FL

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Quote:
Originally Posted by bjornstar View Post
In version 26.6 it now says "Optimizing for CPU architecture: Not Intel and not AMD, L2 cache size: 4 KB"

There is a non-vendor specific way of detecting cache sizes using CPUID that would be preferable. Prime95 v26.6 is now optimizing for 4KB of cache on VIA CPUs when there could be up to 4MB of cache.

Is there someone I can talk to about correctly detecting cache sizes across all x86 vendors?
Prime95 won't be optimized for your architecture, but if you point me to the latest CPUID document for your vendor I'll try to have prime95 detect the cache size properly.
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Old 2011-09-06, 22:07   #44
joeboomz
 
Sep 2011

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Got a brand new Dell server, dual hex-core Xeons. 266 will crash but no crashess yet on 265.

In both versions, the icon popup text in the task bar by the clock is truncated and you won't see the full list of current work. Might be Windows limitation.

Screenshots from both versions attached. The crash is from 266.
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