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Old 2021-08-31, 00:53   #1
Prime95
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Default AlderLake anyone?

Does anyone here have access to an Alder Lake system?

I know prime95 will have some difficulties with the big.little architecture. I'd like to code up some upgrades and have someone test them. If under NDA, I think we can discuss bugs without discussing the architecture specifics.
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Old 2021-08-31, 07:27   #2
JWNoctis
 
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Off topic, but...it's been a while, and I'm kind of surprised that nobody here had brought up the fact that, for whatever reason, Alder Lake apparently won't have AVX-512 support in consumer/client-level processors, including the entire Core lineup.


Which to my understanding would have a non-trivial impact on performance for Prime95, for those who still intend to crunch on their personal machine and planning to buy one of those.



It would be interesting to see some comparison for sure.
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Old 2021-09-03, 06:47   #3
elmor
 
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Hello, I can assist you with testing. You can contact me on the email address I registered with.
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Old 2021-09-03, 12:23   #4
kriesel
 
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Quote:
Originally Posted by JWNoctis View Post
for whatever reason, Alder Lake apparently won't have AVX-512 support in consumer/client-level processors, including the entire Core lineup.

Which to my understanding would have a non-trivial impact on performance for Prime95
It also means that for mprime / prime95, the top of the mersenne.org exponent space will be out of reach. AVX2/FMA3 fft lengths implemented max out at 920.8M.
https://en.wikipedia.org/wiki/Alder_...icroprocessor)

Last fiddled with by Uncwilly on 2021-09-03 at 21:00 Reason: Fixed url
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Old 2021-09-03, 12:53   #5
Zhangrc
 
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Quote:
Originally Posted by kriesel View Post
Off topic, but the right bracket outside the URL tag causes confusion.

You always tell people to check spelling and grammar for every post.

But we must accept that even the best of us make typos and mistakes.

The link should be: (A futile attempt to make this post more relevant )

https://en.wikipedia.org/wiki/Alder_...icroprocessor)

Last fiddled with by Zhangrc on 2021-09-03 at 13:01
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Old 2021-09-03, 13:52   #6
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Quote:
Originally Posted by kriesel View Post
AVX2/FMA3 fft lengths implemented max out at 920.8M.
It is trivial to extend FFT lengths. But only masochists and morons would test these high exponents with today's technology.
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Old 2021-09-03, 13:55   #7
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Quote:
Originally Posted by Zhangrc View Post
The link should be: (A futile attempt to make this post more relevant )

https://en.wikipedia.org/wiki/Alder_...roprocessor%29
Here you go. Replace brackets with their URL escape equivalent.
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Old 2021-09-03, 14:11   #8
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Quote:
Originally Posted by Zhangrc View Post
You always tell people to check spelling and grammar
My bad, I thought a copy/paste of a URL that had already worked for me would be no problem, but apparently it got clobbered.
Quote:
Originally Posted by axn View Post
It is trivial to extend FFT lengths.
Then it should be easy for you to help resolve the known server issue of being unable to handle in its SSE2 instruction set, PRP proof files for exponents >595M requiring longer than 32M fft length. Such exponents can be fully PRP tested in ~ 7 weeks (to ~ 4-5 months for ~1G) on Radeon VIIs including proof file generation, for various test/QA purposes, and benchmarked much quicker for checking run time scaling empirically.

Last fiddled with by kriesel on 2021-09-03 at 14:41
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Old 2021-09-03, 14:55   #9
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Quote:
Originally Posted by kriesel View Post
Then it should be easy for you
Me? No. George, yes. But last I checked he's neither a masochist nor a moron.

Quote:
Originally Posted by kriesel View Post
PRP proof files for exponents >595M requiring longer than 32M fft length. Such exponents can be fully PRP tested in ~ 7 weeks (to ~ 4-5 months for ~1G) on Radeon VIIs including proof file generation, for various test/QA purposes, and benchmarked much quicker for checking run time scaling empirically.
None of these are valid activities in 2021 (IMO). Maybe in 2041, perhaps?
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Old 2021-09-03, 15:36   #10
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Quote:
Originally Posted by axn View Post
George, yes. But last I checked he's neither a masochist nor a moron.
I don't believe Ernst is either, yet ffts up to 512M are now available in Mlucas. (Mainly I think due to Ernst's plan to test F33.) Nor Mihai either, yet ffts up to 120M length and sometimes higher have been available in gpuowl for years. For that matter, CUDALucas had 128M fft length several years ago.

I test while I still can. I'm of an age that, assuming I'm still above the sod then, abilities may have declined considerably in another 20 years. Such testing has already identified the server's current limitation, and some client software issues. Production running is typically wavefronts only. Experimenting with testing widely keeps it interesting. Finding issues early gives George et al maximum time to perhaps address them, before they become an issue at the wavefront, and before their abilities decline due to aging, or whatever calamity might befall them.
Quote:
None of these are valid activities in 2021 (IMO). Maybe in 2041, perhaps?
But we digress. Looking forward to seeing what Alder Lake can bring to the party.
Welcome to the forum Elmor.

Last fiddled with by kriesel on 2021-09-03 at 16:04
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Old 2021-09-05, 08:21   #11
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Quote:
Originally Posted by JWNoctis View Post
Off topic, but...it's been a while, and I'm kind of surprised that nobody here had brought up the fact that, for whatever reason, Alder Lake apparently won't have AVX-512 support in consumer/client-level processors, including the entire Core lineup.

Which to my understanding would have a non-trivial impact on performance for Prime95, for those who still intend to crunch on their personal machine and planning to buy one of those.
A possible explanation I've seen is that both cores need to share a common feature set. As threads get moved around you can't end up with a situation where code needs AVX-512, but it can't be provided by the E cores. The solution for now is to disable AVX-512 where you have E cores present. Unfortunately they have also said you can't get AVX-512 back by disable E cores and run only P cores. I had hoped something smarter could be done at OS level, where for example code needing AVX-512 would only be run on P cores and not touch the E cores at all.

For consumer level CPUs, for bigger FFTs were way into the region where ram bandwidth is limiting. In that scenario, the loss of AVX-512 is less of an impact, and having faster DDR5 speeds would probably result in a net increase to performance.

Where the loss of AVX-512 will be felt more is for those like me who focus on smaller FFTs that are not limited by ram speeds. The open question remains, just what sort of FMA performance can the E cores provide? It might be a case of quantity over quality to provide a possible net positive in performance.
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