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Old 2020-09-18, 21:46   #1
preda
 
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Default The future is 24bit

In light of Nvidia's new GPU launch, it appears we need to find a way of doing big convolutions using SP FP (FP32). This has been an elusive task in the past.

That new GPU has 2x FP32 vs. INT32, and 64x FP32 vs. FP64.
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Old 2020-09-18, 22:48   #2
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AKA "The Holy Grail" :)
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Old 2020-09-18, 23:44   #3
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Quote:
Originally Posted by preda View Post
In light of Nvidia's new GPU launch, it appears we need to find a way of doing big convolutions using SP FP (FP32). This has been an elusive task in the past.

That new GPU has 2x FP32 vs. INT32, and 64x FP32 vs. FP64.
Sorry, I cannot make a connection to 24-bit. FP32 seems to represent 32-bit. FP64 is 64-bit. 2x FP32 suggests 64-bit as wall. Would you care to elaborate a little?
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Old 2020-09-19, 00:26   #4
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Quote:
Originally Posted by storm5510 View Post
Sorry, I cannot make a connection to 24-bit.
https://en.wikipedia.org/wiki/IEEE_754

Last fiddled with by kriesel on 2020-09-19 at 00:26
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Old 2020-09-19, 00:26   #5
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Quote:
Originally Posted by storm5510 View Post
Sorry, I cannot make a connection to 24-bit. FP32 seems to represent 32-bit. FP64 is 64-bit. 2x FP32 suggests 64-bit as wall. Would you care to elaborate a little?
Normal FP32 has 23 bits for the fraction component, 8 for the exponent, and 1 for the sign (+/-). The exponent bits effectively give one more bit of precision, either being all zero or not, meaning FP32 can do INT24 math.
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Old 2020-09-19, 03:14   #6
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Some previous discussion:
https://www.mersenneforum.org/showthread.php?t=23926
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Old 2020-09-19, 05:31   #7
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It sounds like the additional memory usage(and hence memory bandwidth) may be an issue. Would 64x be enough that arithmetic using double-floats would be useful?
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Old 2020-09-19, 05:35   #8
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Years ago I toyed with using two or three 32-bit ints to create a 64 or 96-bit float (no exponent bits -- all mantissa).

I did enough work to prove to myself it was feasible and, at the time, would be about a fast as a double-precision FFT. As nVidia has lowered and lowered the DP-to-SP ratio, it would be a substantial winner now.

An awful lot of code to write though.
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Old 2020-09-19, 08:48   #9
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This post ( https://mersenneforum.org/showpost.p...4&postcount=85 ) suggests that the doubling of fp32 is because they upgraded the int32 units to also do fp32. If int32 and fp32 operations can be freely mixed or if the workload can be split into int32-only and fp32-only operations then there's more bits up for grabs. A split solution should also work on the 20 series as that can do fp32 and int32 concurrently but that is highly memory limited so there may not be a benefit.
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Old 2020-09-19, 09:11   #10
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Quote:
Originally Posted by M344587487 View Post
This post ( https://mersenneforum.org/showpost.p...4&postcount=85 ) suggests that the doubling of fp32 is because they upgraded the int32 units to also do fp32. If int32 and fp32 operations can be freely mixed or if the workload can be split into int32-only and fp32-only operations then there's more bits up for grabs. A split solution should also work on the 20 series as that can do fp32 and int32 concurrently but that is highly memory limited so there may not be a benefit.
Yes. But a number of INT32 is used anyway to do pointer arithmetic, conditional expression, etc; so it's not like when doing a "pure SP" FFT the INT32 is idle.
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Old 2020-09-19, 16:11   #11
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I got to thinking about color palettes. A 24-bit palette is capable of 16,777,215 unique values. This has been in use a long time. Before was 16-bit capable of only 65,536 colors. Whether this is any way relative to the discussion here, I don't know.
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