mersenneforum.org  

Go Back   mersenneforum.org > Great Internet Mersenne Prime Search > Hardware

Reply
 
Thread Tools
Old 2019-06-22, 12:34   #34
nomead
 
nomead's Avatar
 
"Sam Laur"
Dec 2018
Turku, Finland

2·3·5·11 Posts
Default

Quote:
Originally Posted by henryzz View Post
Doesn't it defeat the point of having faster RAM though?
Slightly, but not totally. There's still a slight benefit from using ultra fast RAM on a processor with 12 or 16 cores (two chiplets) but for 6- or 8-core parts with just one CPU chiplet, I'd agree.
nomead is offline   Reply With Quote
Old 2019-06-24, 08:41   #35
M344587487
 
M344587487's Avatar
 
"Composite as Heck"
Oct 2017

3×263 Posts
Default

Quote:
Originally Posted by henryzz View Post
Doesn't it defeat the point of having faster RAM though?
As far as I understand it if you're on a single chiplet CPU it may be a downgrade to go beyond 3733 if you're saturating the bandwidth because of the halved IF. If however you're on a two chiplet CPU like the 12 or 16 core it shouldn't be a problem as you have twice as many IF links to keep up with the faster RAM, each chiplet has its own independent IF link. It looks like ideally the 6 core model should be paired with 3733 RAM and the 12 core should be paired with 5000+.
M344587487 is offline   Reply With Quote
Old 2019-06-24, 12:00   #36
mackerel
 
mackerel's Avatar
 
Feb 2016
UK

25×13 Posts
Default

The possible problem is in the earlier AMD chart where it shows only so much bandwidth potential between the memory controller to the IF bus. That's the possible choke point for high speed ram, unless you run single channel...

I do have some 4000 B-die ram on hand, and will look to test it out as soon as I can. I'd expect the reviewers will also poke around the new ram potential. Even AMD themselves suggest 3600 ram as the performance/price sweet spot.

Last fiddled with by mackerel on 2019-06-24 at 12:01
mackerel is offline   Reply With Quote
Old 2019-06-24, 15:06   #37
nomead
 
nomead's Avatar
 
"Sam Laur"
Dec 2018
Turku, Finland

2·3·5·11 Posts
Default

Quote:
Originally Posted by mackerel View Post
The possible problem is in the earlier AMD chart where it shows only so much bandwidth potential between the memory controller to the IF bus. That's the possible choke point for high speed ram, unless you run single channel...
Yeah but the halved rate should only apply to the Infinityfabric link between the dies, not that internal link inside the I/O die. But yeah, we'll wait and see for benchmarks.
nomead is offline   Reply With Quote
Old 2019-06-24, 19:38   #38
mackerel
 
mackerel's Avatar
 
Feb 2016
UK

25·13 Posts
Default

The diagram didn't seem to make any mention of different IF clocks. The only different bit was the part going to IO block (in die) was double the width.
mackerel is offline   Reply With Quote
Old 2019-06-29, 22:41   #39
Bulldozer
 
Jun 2019

3×7 Posts
Default

Can R9 3950X beat I9-9920X in GIMPS?

Last fiddled with by Bulldozer on 2019-06-29 at 22:43
Bulldozer is offline   Reply With Quote
Old 2019-06-30, 07:32   #40
M344587487
 
M344587487's Avatar
 
"Composite as Heck"
Oct 2017

3×263 Posts
Default

Quote:
Originally Posted by Bulldozer View Post
Can R9 3950X beat I9-9920X in GIMPS?
For wavefront LL/PRP testing no. The CPU is not the bottleneck the memory is, the 9920X uses quad channel memory the 3950X uses dual channel. It would take one miracle of a memory overclock (and the doubled L3 cache being more useful than I think it is when memory is the bottleneck) for the 3950X to even get close.


A 16 core zen 2 Threadripper part on the other hand has access to quad channel memory and I'd expect it to comfortably beat a 9920X.
M344587487 is offline   Reply With Quote
Old 2019-06-30, 08:17   #41
mackerel
 
mackerel's Avatar
 
Feb 2016
UK

6408 Posts
Default

What FFT size is leading edge work at? Could the 3950X with 64MB of cache hold that on socket? My concern is the inter-chiplet bandwidth should cores need cache data on other chiplet. This would have to be tested once available.
mackerel is offline   Reply With Quote
Old 2019-06-30, 13:07   #42
maxzor
 
Apr 2017

1416 Posts
Default

Quote:
Originally Posted by M344587487 View Post
For wavefront LL/PRP testing no.
A 16 core zen 2 Threadripper part on the other hand has access to quad channel memory and I'd expect it to comfortably beat a 9920X.
What is the state-of-the-art hardware for someone looking for the next mersenne prime today? A 9900K? A 9920X? GPGPU? Other (mobile cluster? :) )?
I believe the stickied topics could use some update.
maxzor is offline   Reply With Quote
Old 2019-06-30, 13:33   #43
preda
 
preda's Avatar
 
"Mihai Preda"
Apr 2015

2×677 Posts
Default

Quote:
Originally Posted by maxzor View Post
What is the state-of-the-art hardware for someone looking for the next mersenne prime today? A 9900K? A 9920X? GPGPU? Other (mobile cluster? :) )?
I believe the stickied topics could use some update.
Radeon VII
preda is online now   Reply With Quote
Old 2019-06-30, 16:46   #44
kriesel
 
kriesel's Avatar
 
"TF79LL86GIMPS96gpu17"
Mar 2017
US midwest

47·107 Posts
Default

Quote:
Originally Posted by preda View Post
Radeon VII
Or n of them, for primality testing.
For P-1?
Radeon VII or RTX2080 for TF?
See also https://www.mersenneforum.org/showpo...8&postcount=20 re cost performance.

Last fiddled with by kriesel on 2019-06-30 at 17:09
kriesel is online now   Reply With Quote
Reply

Thread Tools


Similar Threads
Thread Thread Starter Forum Replies Last Post
RX470 and RX460 announced VictordeHolland GPU Computing 0 2016-07-30 13:05
Intel Xeon D announced VictordeHolland Hardware 7 2015-03-11 23:26
Factoring details mturpin Information & Answers 4 2013-02-08 02:43
Euler (6,2,5) details. Death Math 10 2011-08-03 13:49
Larrabee instruction set announced fivemack Hardware 0 2009-03-25 12:09

All times are UTC. The time now is 15:15.

Sun Apr 18 15:15:29 UTC 2021 up 10 days, 9:56, 0 users, load averages: 1.21, 1.45, 1.47

Powered by vBulletin® Version 3.8.11
Copyright ©2000 - 2021, Jelsoft Enterprises Ltd.

This forum has received and complied with 0 (zero) government requests for information.

Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.2 or any later version published by the Free Software Foundation.
A copy of the license is included in the FAQ.