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Old 2018-11-05, 10:35   #1
henryzz
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Default Cascade lake AP

https://www.theregister.co.uk/2018/1..._cascade_lake/

These sound like they have pretty impressive memory bandwidth(12 channels for 48 cores). Why not go for a HBM style solution if you need that many channels?
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Old 2018-11-05, 11:24   #2
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AFAIK these are rushed parts to compete with Epyc so they're essentially two Xeon dies crammed into a single package. No big redesign which is why they have 12 channels and top out at a two socket config instead of four. This is the last big move intel can make until a node shrink, they've already played their hand with consumer parts and this is the server play. It certainly grabs the attention. Yields and temps are a big issue at this level and is no doubt why they top out at 24 cores per die instead of 28. I think it'll be enough to convince some price-insensitive vendors to stick with intel, but they are still going to haemorrhage customers in what is going to be a rough couple of years for them in terms of market share. An unanswered question is how many of the top end parts they actually expect to produce, and the pricing of such a monster.
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Old 2018-11-05, 21:03   #3
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Default Hot hot hot

It will be interesting to see what the TDP is for these parts.

How on Earth can they be cooled effectively ?
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Old 2018-11-05, 21:17   #4
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Quote:
Originally Posted by tServo View Post
It will be interesting to see what the TDP is for these parts.

How on Earth can they be cooled effectively ?
With a chiller!
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Old 2019-03-20, 19:43   #5
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one more month maybe until we see these in the wild...
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Old 2019-04-02, 17:45   #6
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https://www.tomshardware.com/reviews...tane,6061.html
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Old 2019-04-02, 19:05   #7
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Quote:
These new 9000-series chips come packing up to 56 cores and 112 threads
Two 8180 squished together. There was some speculation that they'd get rid of hyperthreading to fit within other constraints, nice to have confirmation it's still present.


Quote:
A dual-socket server presents itself as a quad-socket server to the host, meaning the four NUMA nodes appear as four distinct CPUs, but the dual-die topology poses latency challenges for access to 'far' memory banks. Intel says it has largely mitigated the problem with a single-hop routing scheme that provides 79ns of latency for near memory and 130ns for far memory access.
It'll be interesting to see what the near and far memory latency actually means. Does far mean the other processor on the die, the other die or both? It could be one of the only ways this is better than two 8180.
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Old 2019-04-02, 19:14   #8
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Quote:
Originally Posted by M344587487 View Post
Two 8180 squished together. There was some speculation that they'd get rid of hyperthreading to fit within other constraints, nice to have confirmation it's still present.

It'll be interesting to see what the near and far memory latency actually means. Does far mean the other processor on the die, the other die or both? It could be one of the only ways this is better than two 8180.
Sounds like it's just a fat version of the Ryzen CCX-based dies.
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Old 2019-04-03, 20:05   #9
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Quote:
Originally Posted by tServo View Post
It will be interesting to see what the TDP is for these parts.

How on Earth can they be cooled effectively ?
It ranges from 250 to 400 watts: https://pcgamer.com/intel-just-unvei...for-gaming-yet

Last fiddled with by ixfd64 on 2019-04-03 at 20:06
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Old 2019-04-03, 21:38   #10
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Quote:
Originally Posted by Mysticial View Post
Sounds like it's just a fat version of the Ryzen CCX-based dies.
Sort of. Saying CCX could be confusing as I believe each zen die has two CCX's with equal access to either channel of dual channel RAM, the memory controller is independent of the CCX's and the intra-die latencies are from the CCX's being somewhat distinct. A closer comparison of 8180 to monster lake would be how Threadripper and Epyc have multiple zen dies, you can call them squished together Ryzen's and not be far off. They don't share cache etc but also don't have equal access to system memory.

They've gone from offering up to four socket systems with 28 cores per socket to up to two socket systems with 56 cores per socket. Aside from the perception of competing with the upcoming 64 core Epyc processors these are the potential differences I can spot:
  • Possibly lower latency between dies on the same package
  • An excuse to transition to more competitive pricing compared to the 8180
  • A smaller form factor for density at the expense of having to liquid cool the top end part
  • Update to the latest ++++ process for better thermals, clocks and rated memory speeds
  • It might be a typo but both (8180 9282) specs say they have two AVX-512 units. Could this be a regression?
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Old 2019-04-04, 08:35   #11
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Quote:
Originally Posted by M344587487 View Post
It might be a typo but both (8180 9282) specs say they have two AVX-512 units. Could this be a regression?
Unless I'm missing something here, 2 units per core is the full fat implementation which is good if you can tame the thermals. Lesser models like the low end Xeons might only have one unit per core.

On that note, I wonder if the TDP is under AVX-512 load? Under AVX2 or lesser loads it is probably a lot lower, unless they use that to turbo much harder which might reduce the gap.
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