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Old 2002-09-05, 06:06   #1
crash893
 
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Default 64bit cpu's

is there going to be a new client for the new amd hammer that will run with a 64 bit prosses

if so when
if not why
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Old 2002-09-05, 09:48   #2
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Dunno... :)

But 64-bit doesn't mean it will be better...

I ran mlucas on my 64-bit Suns (200MHz Ultra 1, 270MHz Ultra 5 & 500MHz Netra X1) and it performed like crap... It wasn't the fault of the program either... Some 64-bit boxes do okay with it, like some Alphas...

Hopefully AMD adds SSE2 in soon...
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Old 2002-09-05, 15:04   #3
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Screaming SIMD-E 2 will be a feature of all hammer and, going forward, the ninth generation of processor architecture as well.
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Old 2002-09-05, 19:03   #4
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If the price is reasonable on the CPU, I'll buy one one day and write an updated client. As I understand it, the only new feature that prime95 will be able to really use is 8 more SSE2 registers. 64-bit integers might speed up trial factoring. I'm not sure what the L2 cache and data TLBs will be, but they are an important part of whether prime95 will perform well or not.
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Old 2002-09-05, 19:15   #5
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there not going to be out for a while

so youll need a new mobo for the hammer

the hammer its self

and a 64 bit os linux has one already but there is no ms one yet

its slated to come out in 2003 so you got a while yet
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Old 2002-09-06, 19:53   #6
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Quote:
Originally Posted by Prime95
As I understand it, the only new feature that prime95 will be able to really use is 8 more SSE2 registers. 64-bit integers might speed up trial factoring. I'm not sure what the L2 cache and data TLBs will be, but they are an important part of whether prime95 will perform well or not.
Wouldnt the floating point be 64 bit as well on a 64 bit cpu? That should help a lot unless I am missing something obvious.

For the L2 and TLB, no doubt prime95 cares a lot. But does primes95, as it is today, touch the TLB or cache policy in anyway? I would be surprised if it does.
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Old 2002-09-06, 20:52   #7
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Quote:
Originally Posted by ebx
Wouldnt the floating point be 64 bit as well on a 64 bit cpu? That should help a lot unless I am missing something obvious.

For the L2 and TLB, no doubt prime95 cares a lot. But does primes95, as it is today, touch the TLB or cache policy in anyway? I would be surprised if it does.
Floating point units are already 64 bits. Now, if the Hammer came out with a 128-bit FPU, that would be wonderful. Of course they won't since only one program in a million would find this feature useful. They have better uses for the silicon.

Prime95 does pound the TLB cache too. That's because a 1M FFT has its data spread over 2048 pages. That's much more than will fit in the current 64 entry TLB cache.
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Old 2002-09-06, 21:19   #8
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The ALL P4 does in fact have 128 entries TLB. There was a bug with the B-0 stepping that it reports only 64 TLB but in fact it has 128.

http://www.intel.com/design/processor/future/manuals/Cpuid_supplement.pdf
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Old 2002-09-06, 21:20   #9
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Quote:
Originally Posted by Prime95
Floating point units are already 64 bits. Now, if the Hammer came out with a 128-bit FPU, that would be wonderful. Of course they won't since only one program in a million would find this feature useful. They have better uses for the silicon.

Prime95 does pound the TLB cache too. That's because a 1M FFT has its data spread over 2048 pages. That's much more than will fit in the current 64 entry TLB cache.
AMD released their 5-vol Hammer document set a couple of days ago. I didnt read the details but it does have a 128bit media and scientific programming instruction set. In x87 mode, however, the FPU registers are still 80 bits. If the floating point stays at 32x32(that is the 64 bits you quote above, I guess), it wouldnt have been a true 64 bit chip.

How big is a 1M FFT table? If you ask in bigger trunks, why would it need 2048 pages? Loading pages are so expensive. Ok, maybe it is the OS that only supports a unified page size. What is window's page size, a stone age 4k?
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Old 2002-09-06, 21:27   #10
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Quote:
Originally Posted by xtreme2k
The ALL P4 does in fact have 128 entries TLB. There was a bug with the B-0 stepping that it reports only 64 TLB but in fact it has 128.
My understanding is 128 instruction TLBs and 64 data TLBs.
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Old 2002-09-06, 21:29   #11
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Quote:
Originally Posted by ebx
How big is a 1M FFT table? If you ask in bigger trunks, why would it need 2048 pages? Loading pages are so expensive. Ok, maybe it is the OS that only supports a unified page size. What is window's page size, a stone age 4k?
A 1M FFT uses up 8MB. Linux/Windows use the stone age 4KB page size because that is what the Intel chip supports.
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