mersenneforum.org  

Go Back   mersenneforum.org > Great Internet Mersenne Prime Search > Hardware

Reply
 
Thread Tools
Old 2021-06-02, 09:17   #12
M344587487
 
M344587487's Avatar
 
"Composite as Heck"
Oct 2017

37D16 Posts
Default

Quote:
Originally Posted by mackerel View Post
...
Hot info from Ian Cutress of Ananadtech: "Confirmed with AMD that V-Cache will be coming to Ryzen Zen 3 products, with production at end of year."
https://twitter.com/IanCutress/statu...66139769602058

This is pure guess on my part, extra cache Zen3 parts may be used to push back the Zen4 release and smooth out supply issues transitioning to 5nm. Probably also used as a stall tactic to wait and see if and how far intel fails to deliver with their next gen. I wonder if 7nm SRAM can and will be paired with 5nm chiplets in the future.
M344587487 is offline   Reply With Quote
Old 2021-06-02, 10:05   #13
mackerel
 
mackerel's Avatar
 
Feb 2016
UK

23·5·11 Posts
Default

Zen 4 being later than sooner is an often discussed possibility, but it wasn't so much due to 5nm as DDR5 as the given reason. If Intel go DDR5 first, they'll take the early adopter hit on pricing while they gear up the market, then AMD can stroll along and pick up once it is more established. We see that kind of move a lot from AMD, don't know how much is due to choice or necessity though.
mackerel is offline   Reply With Quote
Old 2021-06-02, 18:51   #14
nordi
 
Dec 2016

7816 Posts
Default

Quote:
Originally Posted by mackerel View Post
I'm wondering where the 2 TB/s claim comes from. Can 8 cores move data in/out of that cache at that speed? Or it is a theoretical maximum based on stacking? I don't have numbers for Zen 3 currently, what does that do as currently sold? I did a quick Aida64 on my 8 core Cezanne and that's only 100GB/s copy in L3.
This graphic from Anandtech's Zen3 deep dive shows "32B / cycle" as L3 bandwith per core. At 4Ghz, that's 128GB/s, which is in line with your 100. For 16 cores, the total bandwidth is 16*128GB/s = 2TB/s. Maybe that's where the number comes from. Anyway, the cores themselves could use up the bandwidth already, so the question is if the L3 cache can deliver it.

For anyone that wants to see Lisa Su's original announcent, it's here. Not sure if all the articles that were written are based on additional sources, or just those 5 minutes of video.
nordi is offline   Reply With Quote
Old 2021-06-08, 18:46   #15
M344587487
 
M344587487's Avatar
 
"Composite as Heck"
Oct 2017

19·47 Posts
Default

A bigger deal for general use might be iGPU's, currently they are what a typical person will encounter memory bandwidth limitations with if anything and the improvement could be sizeable. A unified cache for CPU and GPU is probably too complicated (or is it? If they want to resume pursuing HSA it may be a natural progression), but who's to say that the SRAM can't be attached to the iGPU as infinity cache instead of the CPU as v-cache? Better yet have a bios boot option to set the 64MiB SRAM stack as either V-cache or infinity cache, given how modular AMD has been lately I would bet that the two technologies largely differ only in the controller used.

Currently you can use a Ryzen APU for "good enough at 720P, mostly" gaming. It would be nice if the baseline can jump to "good enough at 1080P, mostly".
M344587487 is offline   Reply With Quote
Old 2021-11-09, 01:57   #16
JWNoctis
 
"J. W."
Aug 2021

5×7 Posts
Default

More news coming out: 64-Core Zen 3 EPYC with 96MiB * 8 L3 cache, 10% overhead to overall latency, vast performance improvement projected for enterprise workload.

Supposedly they also have preview instances on Azure now.
JWNoctis is offline   Reply With Quote
Old 2022-03-16, 03:05   #17
JWNoctis
 
"J. W."
Aug 2021

5×7 Posts
Default

So it's coming out soon. $100 listed-price premium for lower base and boost clock, apparently no overclocking, and 64MiB more of L3 cache. Enough L3 for wavefront PRP for the foreseeable future, but may well hit L3 ringbus limit.

Workloads exceeding L3 size may well end up slower due no IF/MMU overclocking.

Curious.

https://www.techpowerup.com/292256/a...esign-at-isscc
https://arstechnica.com/gadgets/2022...il-20-for-449/
JWNoctis is offline   Reply With Quote
Old 2022-03-18, 04:49   #18
JWNoctis
 
"J. W."
Aug 2021

5·7 Posts
Default

Correction: They do support IF/MMU overclocking after all. Enticing.
JWNoctis is offline   Reply With Quote
Old 2022-03-21, 16:23   #19
M344587487
 
M344587487's Avatar
 
"Composite as Heck"
Oct 2017

19·47 Posts
Default

The server version reviews are out, some of the HPC uplift looks very tasty: https://www.phoronix.com/scan.php?pa...yc-7773x-linux
M344587487 is offline   Reply With Quote
Old 2022-05-06, 07:44   #20
Mark Rose
 
Mark Rose's Avatar
 
"/X\(‘-‘)/X\"
Jan 2013

23·32·41 Posts
Default

As expected, the 5800X3D does better at large FFTs: https://www.mersenneforum.org/showpo...&postcount=872
Mark Rose is offline   Reply With Quote
Reply

Thread Tools


Similar Threads
Thread Thread Starter Forum Replies Last Post
Is "mung" or "munged" a negative word in a moral sense? Uncwilly Lounge 15 2020-04-14 18:35
Stockfish game: "Move 8 poll", not "move 3.14159 discussion" MooMoo2 Other Chess Games 5 2016-10-22 01:55
"Master" and "helper" threads Madpoo Software 0 2016-09-08 01:27
Aouessare-El Haddouchi-Essaaidi "test": "if Mp has no factor, it is prime!" wildrabbitt Miscellaneous Math 11 2015-03-06 08:17
Would Minimizing "iterations between results file" may reveal "is not prime" earlier? nitai1999 Software 7 2004-08-26 18:12

All times are UTC. The time now is 06:23.


Fri May 27 06:23:52 UTC 2022 up 43 days, 4:25, 0 users, load averages: 2.81, 1.90, 1.31

Powered by vBulletin® Version 3.8.11
Copyright ©2000 - 2022, Jelsoft Enterprises Ltd.

This forum has received and complied with 0 (zero) government requests for information.

Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.2 or any later version published by the Free Software Foundation.
A copy of the license is included in the FAQ.

≠ ± ∓ ÷ × · − √ ‰ ⊗ ⊕ ⊖ ⊘ ⊙ ≤ ≥ ≦ ≧ ≨ ≩ ≺ ≻ ≼ ≽ ⊏ ⊐ ⊑ ⊒ ² ³ °
∠ ∟ ° ≅ ~ ‖ ⟂ ⫛
≡ ≜ ≈ ∝ ∞ ≪ ≫ ⌊⌋ ⌈⌉ ∘ ∏ ∐ ∑ ∧ ∨ ∩ ∪ ⨀ ⊕ ⊗ 𝖕 𝖖 𝖗 ⊲ ⊳
∅ ∖ ∁ ↦ ↣ ∩ ∪ ⊆ ⊂ ⊄ ⊊ ⊇ ⊃ ⊅ ⊋ ⊖ ∈ ∉ ∋ ∌ ℕ ℤ ℚ ℝ ℂ ℵ ℶ ℷ ℸ 𝓟
¬ ∨ ∧ ⊕ → ← ⇒ ⇐ ⇔ ∀ ∃ ∄ ∴ ∵ ⊤ ⊥ ⊢ ⊨ ⫤ ⊣ … ⋯ ⋮ ⋰ ⋱
∫ ∬ ∭ ∮ ∯ ∰ ∇ ∆ δ ∂ ℱ ℒ ℓ
𝛢𝛼 𝛣𝛽 𝛤𝛾 𝛥𝛿 𝛦𝜀𝜖 𝛧𝜁 𝛨𝜂 𝛩𝜃𝜗 𝛪𝜄 𝛫𝜅 𝛬𝜆 𝛭𝜇 𝛮𝜈 𝛯𝜉 𝛰𝜊 𝛱𝜋 𝛲𝜌 𝛴𝜎𝜍 𝛵𝜏 𝛶𝜐 𝛷𝜙𝜑 𝛸𝜒 𝛹𝜓 𝛺𝜔