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Old 2016-06-22, 17:41   #12
science_man_88's Avatar
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Jul 2009

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Originally Posted by Antonio View Post
So what magic do they use to transfer instructions and data into/out of the processors?
well my point is that technically they can hold it in one processor until they want to use it in another. so really all they need is the lines that would normally transfer it to a ram module I bet.
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Old 2016-06-22, 22:04   #13
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Sep 2002

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The power dissipation per operation is "5.8 pJ/Op @0.56V, 115MHz" from the bottom of this table.

The pertinent reference for the table entry is:
[64] Brent Bohnenstiehl, Aaron Stillmaker, Jon Pimentel, Timothy Andreas, Bin Liu, Anh Tran, Emmanuel Adeagbo and Bevan Baas,"A 5.8 pJ/Op 115 Billion Ops/sec, to 1.78 Trillion Ops/sec 32nm 1000-Processor Array," IEEE Symposium on VLSI Circuits, Honolulu, HI, June 2016.

This is U.C. Davis' VLSI computer lab

The table mentions a clock speed of 1.782 GHz@1.1 V.
The total aggregate operations per second spread from 1.15 x 1011 to 1.78 x 1012 may pertain to how many clock cycles an underlying core CPU operation takes. The VLSI lab mentions two previous generations of asynchronous CPU arrays. These previous generations used customized processors.

The second generation was "AsAP 2. A second generation 65 nm CMOS design contains 167 processors with dedicated FFT, Viterbi, and video motion estimation processors; 16 KB shared memories; and long-distance inter-processor interconnect."

The article mentioned IBM. IBM previously partnered in another apparently unrelated 1000 CPU project with a startup a decade ago that also used the name Kilocore.

Last fiddled with by only_human on 2016-06-22 at 22:12 Reason: s/Berkeley/Davis/. :-o
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