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Old 2013-03-18, 14:43   #1
kracker
 
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Default Haswell Preview Benchmark

Just saw this.
http://www.tomshardware.com/reviews/...ance,3461.html
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Old 2013-03-18, 18:27   #2
Dubslow
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Hmm... now George, how useful was TSX for multithreaded tests....?
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Old 2013-03-19, 01:33   #3
Prime95
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Quote:
Originally Posted by Dubslow View Post
Hmm... now George, how useful was TSX for multithreaded tests....?
Hadn't thought about it - I suspect useless.
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Old 2013-03-23, 20:57   #4
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Why doesn't Intel send engineering samples to you? Your highly optimized software is one of the hallmarks for testing Intel's microprocessors

Consider asking them for review or engineering samples; I think Prime95 has clout similar to the top hardware review websites. They get Intel's latest parts early in exchange for a NDA.
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Old 2013-03-24, 10:48   #5
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Quote:
Originally Posted by E_tron View Post
Why doesn't Intel send engineering samples to you? Your highly optimized software is one of the hallmarks for testing Intel's microprocessors

Consider asking them for review or engineering samples; I think Prime95 has clout similar to the top hardware review websites. They get Intel's latest parts early in exchange for a NDA.
I guess one Thomas Nicely was enough for them...

Luigi
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Old 2013-03-26, 17:05   #6
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Quote:
Originally Posted by E_tron View Post
Why doesn't Intel send engineering samples to you? Your highly optimized software is one of the hallmarks for testing Intel's microprocessors
I'm not sure that'd be a favor to George: it looks like the ES Tom's Hardware put their hands on was not fully tuned given the memory bandwidth (17 GB/s vs 20.4 for Sandy and Ivy Bridge) :)
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Old 2013-05-30, 19:40   #7
ewmayer
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The following snip of the TomsHW piece has me confused:
Quote:
Floating-point performance also enjoys a significant speed-up from Intel’s first implementation of FMA3 (AMD’s Bulldozer design supports FMA4, while Piledriver supports both the three- and four-operand versions). The Ivy and Sandy Bridge-based processors utilize AVX-optimized code paths, falling quite a bit behind at the same clock rate.

Why do doubles seem to speed up so much more than floats on Haswell? The code path for FMA3 is actually latency-bound. If we were to turn off FMA3 support altogether in Sandra’s options and used AVX, the scaling proves similar.
That seems to say they got a nice speedup for double-math on haswell, but that it's not in fact from use of FMA. Huh?

Also, it seems faster ddr4 RAM is something like a year away - George and I were discussing this last week, he wrote:
Quote:
I'd bet DDR4 Haswell is only going to be available in pricy "enthusiast" configurations.

I'm really not up on which DDR3 memory will run the fastest. I'll need to research this.
If one has a decently-fast sandy or ivy bridge setup, will the ddr3 from that likely be usable with haswell, or not?
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Old 2013-05-30, 20:26   #8
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Likely usable, although not optimal. Just how non-optimal remains to be discovered...
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Old 2013-05-31, 18:16   #9
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Performance-wise I can't really see how much of an improvement one will see from DDR4 over DDR3. There aren't many real applications limited by memory speed.

One the other hand, if Haswell or Haswell-E (or even Ivy Bridge-E) use DDR4, I would say it would be highly unlikely that the modules will even fit. DDR2 and DDR3 don't both fit in the same DIMM slots.
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Old 2013-05-31, 18:23   #10
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Quote:
Originally Posted by TheMawn View Post
Performance-wise I can't really see how much of an improvement one will see from DDR4 over DDR3. There aren't many real applications limited by memory speed.
Prime95 is, in higher end cpu's.
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Old 2013-05-31, 19:31   #11
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Quote:
Originally Posted by TheMawn View Post
Performance-wise I can't really see how much of an improvement one will see from DDR4 over DDR3. There aren't many real applications limited by memory speed.
Both George's code and mine show clear bandwidth-constrainedness in the relatively modest speedup (1.3-1.4x) seen in going from SSE2 to AVX assembler on the *y Bridge processors. The FMA capability of the AVX2-supporting *well CPUs will be of little use to us if the memory subsystem can't keep the CPU fed.

Quote:
One the other hand, if Haswell or Haswell-E (or even Ivy Bridge-E) use DDR4, I would say it would be highly unlikely that the modules will even fit. DDR2 and DDR3 don't both fit in the same DIMM slots.
I never suggested that ddr3 and ddr4 would be supported interchangeably. I fully expect separate MoBo designs for ddr4 when it arrives. I suppose it's possible some MoBos might have separate slot arrays for both kinds, but that seems like a poor marketing choice for a MoBo manufacturer.
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