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#1079 | |
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6809 > 6502
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Aug 2003
101×103 Posts
3·7·17·31 Posts |
Quote:
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#1080 | |
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"TF79LL86GIMPS96gpu17"
Mar 2017
US midwest
11110100011112 Posts |
Quote:
https://www.mersenne.org/report_LL/?...p_hi=109512329 https://www.intel.com/content/www/us...fications.html Both were prime95, but different versions; neither shows an error code. It would have been better if the second run had been PRP/GEC/proof-gen, by a software version that supports it. And by different user. By different software. Took: DoubleCheck=109512329,77,1 @ChZ: please upgrade prime95 instances to ~v30.8b17 where practical. Do you have any interim res64s to share by PM from either previous LL run? (10M or 20M spacings would be fine) Last fiddled with by kriesel on 2023-03-29 at 14:28 |
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#1081 |
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"TF79LL86GIMPS96gpu17"
Mar 2017
US midwest
782310 Posts |
Confirmed first bad, second good.
https://www.mersenne.org/report_expo...=1&swversion=1 Reasoning provided by PM appears confirmed. |
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#1083 |
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6809 > 6502
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Aug 2003
101×103 Posts
3·7·17·31 Posts |
Just a note, there is a new TC candidate. Also, I have been checking every few days the list for TC and the 1LL+1PRP list. Both have been zero entries of late. Once we get those SDC's done, we will be in a glorious era.
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#1084 | |||
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"TF79LL86GIMPS96gpu17"
Mar 2017
US midwest
7,823 Posts |
Quote:
Quote:
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Consider 333043493 taken, as LLTC which I had already under way on Gpuowl & Radeon VII while prime95 progress was blocked earlier. (I'll queue it in a prime95 worktodo shortly.) See https://mersenneforum.org/showpost.p...1&postcount=29 or here or here or previous discussion (in this thread at the time, since relocated) for why LL in just a few specific documented cases. Also see https://mersenneforum.org/showpost.p...&postcount=862 and related posts in that thread for the LLDC run issue, entirely conducted on ECC ram systems. I'm still cleaning up after my own runs: https://mersenneforum.org/showpost.p...&postcount=803 Last fiddled with by kriesel on 2023-03-30 at 22:59 |
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#1085 | |
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6809 > 6502
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Aug 2003
101×103 Posts
1106710 Posts |
Quote:
I think that the point that there were a lot of errors in the initial 100M LL's has been well proven.
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#1086 |
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Jul 2004
Milan, Ita
22×32×7 Posts |
This time for a QC: requesting (as always, LL only, please) for this one:
Code:
DoubleCheck=66478897,75,1 |
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#1087 |
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Aug 2002
North San Diego Coun
821 Posts |
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#1088 | |
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"TF79LL86GIMPS96gpu17"
Mar 2017
US midwest
1E8F16 Posts |
Quote:
If I remember correctly, it was you that criticized the thin statistical basis of attachment 3 of https://www.mersenneforum.org/showpo...6&postcount=14 on the basis of too-small sample size. (Or perhaps it was about polls. Or both.) Today, ~21 months later, for https://www.mersenne.org/report_LL/?...2192810&unv=-1 52 exponents verified & not factored, with 117 tests total, up to 4 per exponent; and 15 listed as bad; so 15 bad of 132 tests of known status; 11.36% bad, compared to the 13.7% found in June 2021 with smaller sample size (7 bad, 44 matching tests, 21 exponents), both cases of which exclude exponents with only suspect or conflicting residues requiring a TC or higher to resolve which residues are wrong. We have slightly better statistics now, but still +-5.4% for 95% confidence interval per https://calculator-online.net/margin...or-calculator/ |
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