Ryzen 9 7900 non x -variant

[firejuggler]

https://www.tomshardware.com/news/am...600-cpu-review

Originally Posted by tomshardware

AMD's $429 twelve-core Ryzen 9 7900, $329 eight-core Ryzen 7 7700, and $229 six-core Ryzen 5 7600 come to market as the first 'Non-X' Ryzen
models for the company's new AM5 platform for Zen 4 processors. As we've seen with AMD's previous-gen lower-power models, these 65W
models offer the same core counts and cache as their full-fledged X-series counterparts but come with lower clock speeds and a lower price point.

[Mark Rose]

On the desktop, what we do is usually memory bandwidth constrained anyway, so running at a lower clock with lower power consumption is fine.

The 7800X3D is more interesting.

I'm kind of disappointed the 7950X3D has extra cache on only one chiplet.

[M344587487]

That is a bummer, (kind of) halving the high platform cost by having 1x7950x3d instead of 2x7800x3d would be nice. There will likely be scheduler issues on Linux with the 7950x3d, it took intel a while to get the P+E cores working well and out of the two companies they are the ones known for more timely FOSS support (then again intels solution was probably a lot more complex). Maybe it won't matter so much for the 7950x3d as the difference in the asymmetric cores is only the cache AFAIK, but for workloads that do greatly benefit from the cache the user will likely have to manually set affinities for the best performance.

The 7900 and 7800x3d are the most interesting sku's IMO, depending on price. 12 strong cores would be very good at hosting VM's.

[henryzz]

As far as I can see online on the non-3d cpus the L3 cache is a victim cache and each CCD will only write to its own half of the L3 cache but can read from both(presumably with a latency penalty?). Presumably, this holds for Zen4-3d which might mean that it is still useful for both CCDs assuming only one is writing to the cache. This could be an interesting optimisation problem having one CCD do 3x as much writing to L3 cache.

I suspect the 7900 is possibly the most efficient option. As far as I can tell it is possible to overclock it to near the level of the 7900X but in reality, the clock rate hit is dwarfed by the reduction in power usage.

[Mark Rose]

Originally Posted by henryzz

As far as I can see online on the non-3d cpus the L3 cache is a victim cache and each CCD will only write to its own half of the L3 cache but can read from both(presumably with a latency penalty?). Presumably, this holds for Zen4-3d which might mean that it is still useful for both CCDs assuming only one is writing to the cache. This could be an interesting optimisation problem having one CCD do 3x as much writing to L3 cache.

I suspect the 7900 is possibly the most efficient option. As far as I can tell it is possible to overclock it to near the level of the 7900X but in reality, the clock rate hit is dwarfed by the reduction in power usage.

In Zen, the L3 is always a victim cache. As far as reading values from other chiplets, AMD uses the MOESI protocol. This is different protocol than Intel uses.

The 7900 may be the most efficient. If one chiplet's workload fits entirely in the bigger L3 cache, the other chiplet can get full read bandwidth from the main memory for working on its own assignment. Though just 6 cores is likely to saturate the DDR5 memory bandwidth with AVX512.

I think the real winner will be whatever 96 core Genoa-X CPU comes out. With 96 MB L3 per chiplet, each chiplet running at 30 watts or so, it'll be a throughput and efficiency monster.