Prime95 version 29.6/29.7/29.8 - Page 26

Bigeagle · 2019-06-06, 13:10

Well, no. I did it now for the p95v298b3.win64.zip as the checksum is provided in the download section and it matches
here - ftp://mersenne.org/gimps/ - i didn't find any checksums so i don't know how to check the older versions.

Prime95 · 2019-06-06, 14:32

Quote:

Originally Posted by Bigeagle

I recently got a ryzen 2600 to test and play with from time to time and i tried to use prime95 for some stress testing like i always do. But on the newer Versions i get errors right after the start as long as i select 'just stress testing' or 'join gimps' in the first startup dialogue.
p95v298b3.win64

the error code is the same for p95v298b3.win32, p95v297b1.win64, p95v296b7.win64
p95v295b9.win64 worked/is wiorking

Clearly a program bug.

Please run a benchmark in p95v295b9.win64. Abort it as soon as it starts. In results.txt (or results.bench.txt) you should see hwloc's dump of the Ryzen architecture. Can you post that please?

Bigeagle · 2019-06-06, 16:55

AMD Ryzen 5 2600 Six-Core Processor
CPU speed: 3792.95 MHz, 6 hyperthreaded cores
CPU features: 3DNow! Prefetch, SSE, SSE2, SSE4, AVX, AVX2, FMA
L1 cache size: 12x32 KB, L2 cache size: 12x512 KB, L3 cache size: 12x16 MBL1 cache line size: 64 bytes
L2 cache line size: 64 bytes
Machine topology as determined by hwloc library:
Machine#0 (total=28201712KB, Backend=Windows, hwlocVersion=2.0.3, ProcessName=prime95.exe)
Package (total=28201712KB, CPUVendor=AuthenticAMD, CPUFamilyNumber=23, CPUModelNumber=8, CPUModel="AMD Ryzen 5 2600 Six-Core Processor ", CPUStepping=2)
Core (cpuset: 0x00000003)
L3 (size=16384KB, linesize=64, ways=16, Inclusive=0)
L2 (size=512KB, linesize=64, ways=8, Inclusive=1)
L1d (size=32KB, linesize=64, ways=8, Inclusive=0)
PU#0 (cpuset: 0x00000001)
L3 (size=16384KB, linesize=64, ways=16, Inclusive=0)
L2 (size=512KB, linesize=64, ways=8, Inclusive=1)
L1d (size=32KB, linesize=64, ways=8, Inclusive=0)
PU#1 (cpuset: 0x00000002)
Core (cpuset: 0x0000000c)
L3 (size=16384KB, linesize=64, ways=16, Inclusive=0)
L2 (size=512KB, linesize=64, ways=8, Inclusive=1)
L1d (size=32KB, linesize=64, ways=8, Inclusive=0)
PU#2 (cpuset: 0x00000004)
L3 (size=16384KB, linesize=64, ways=16, Inclusive=0)
L2 (size=512KB, linesize=64, ways=8, Inclusive=1)
L1d (size=32KB, linesize=64, ways=8, Inclusive=0)
PU#3 (cpuset: 0x00000008)
Core (cpuset: 0x00000030)
L3 (size=16384KB, linesize=64, ways=16, Inclusive=0)
L2 (size=512KB, linesize=64, ways=8, Inclusive=1)
L1d (size=32KB, linesize=64, ways=8, Inclusive=0)
PU#4 (cpuset: 0x00000010)
L3 (size=16384KB, linesize=64, ways=16, Inclusive=0)
L2 (size=512KB, linesize=64, ways=8, Inclusive=1)
L1d (size=32KB, linesize=64, ways=8, Inclusive=0)
PU#5 (cpuset: 0x00000020)
Core (cpuset: 0x000000c0)
L3 (size=16384KB, linesize=64, ways=16, Inclusive=0)
L2 (size=512KB, linesize=64, ways=8, Inclusive=1)
L1d (size=32KB, linesize=64, ways=8, Inclusive=0)
PU#6 (cpuset: 0x00000040)
L3 (size=16384KB, linesize=64, ways=16, Inclusive=0)
L2 (size=512KB, linesize=64, ways=8, Inclusive=1)
L1d (size=32KB, linesize=64, ways=8, Inclusive=0)
PU#7 (cpuset: 0x00000080)
Core (cpuset: 0x00000300)
L3 (size=16384KB, linesize=64, ways=16, Inclusive=0)
L2 (size=512KB, linesize=64, ways=8, Inclusive=1)
L1d (size=32KB, linesize=64, ways=8, Inclusive=0)
PU#8 (cpuset: 0x00000100)
L3 (size=16384KB, linesize=64, ways=16, Inclusive=0)
L2 (size=512KB, linesize=64, ways=8, Inclusive=1)
L1d (size=32KB, linesize=64, ways=8, Inclusive=0)
PU#9 (cpuset: 0x00000200)
Core (cpuset: 0x00000c00)
L3 (size=16384KB, linesize=64, ways=16, Inclusive=0)
L2 (size=512KB, linesize=64, ways=8, Inclusive=1)
L1d (size=32KB, linesize=64, ways=8, Inclusive=0)
PU#10 (cpuset: 0x00000400)
L3 (size=16384KB, linesize=64, ways=16, Inclusive=0)
L2 (size=512KB, linesize=64, ways=8, Inclusive=1)
L1d (size=32KB, linesize=64, ways=8, Inclusive=0)
PU#11 (cpuset: 0x00000800)
Prime95 64-bit version 29.5, RdtscTiming=1

I assume this is what you meant.

Prime95 · 2019-06-06, 21:54

Quote:

Originally Posted by Bigeagle

I assume this is what you meant.

Yes.

I'm pretty sure you are a victim of bug #19 in the second post of this thread. Since I have not released a win64 29.8 build 4, the only workaround would be to add "NumCpus=12" to local.txt.

But first --- I don't like hwloc's description of your hardware. Please go to
https://www.open-mpi.org/software/hwloc/v2.0/ and get 2.0.4rc1. Rerun the benchmark and see if the hwloc description changes for the better.

Bigeagle · 2019-06-07, 07:38

The Workaround worked. I just get offered to run 24 workers by default :)

AMD Ryzen 5 2600 Six-Core Processor
CPU speed: 3473.40 MHz, 6 hyperthreaded cores
CPU features: 3DNow! Prefetch, SSE, SSE2, SSE4, AVX, AVX2, FMA
L1 cache size: 12x32 KB, L2 cache size: 12x512 KB, L3 cache size: 12x16 MBL1 cache line size: 64 bytes
L2 cache line size: 64 bytes
Machine topology as determined by hwloc library:
Machine#0 (total=27862856KB, Backend=Windows, hwlocVersion=2.0.4rc1, ProcessName=prime95.exe)
Package (total=27862856KB, CPUVendor=AuthenticAMD, CPUFamilyNumber=23, CPUModelNumber=8, CPUModel="AMD Ryzen 5 2600 Six-Core Processor ", CPUStepping=2)
Core (cpuset: 0x00000003)
L3 (size=16384KB, linesize=64, ways=16, Inclusive=0)
L2 (size=512KB, linesize=64, ways=8, Inclusive=1)
L1d (size=32KB, linesize=64, ways=8, Inclusive=0)
PU#0 (cpuset: 0x00000001)
L3 (size=16384KB, linesize=64, ways=16, Inclusive=0)
L2 (size=512KB, linesize=64, ways=8, Inclusive=1)
L1d (size=32KB, linesize=64, ways=8, Inclusive=0)
PU#1 (cpuset: 0x00000002)
Core (cpuset: 0x0000000c)
L3 (size=16384KB, linesize=64, ways=16, Inclusive=0)
L2 (size=512KB, linesize=64, ways=8, Inclusive=1)
L1d (size=32KB, linesize=64, ways=8, Inclusive=0)
PU#2 (cpuset: 0x00000004)
L3 (size=16384KB, linesize=64, ways=16, Inclusive=0)
L2 (size=512KB, linesize=64, ways=8, Inclusive=1)
L1d (size=32KB, linesize=64, ways=8, Inclusive=0)
PU#3 (cpuset: 0x00000008)
Core (cpuset: 0x00000030)
L3 (size=16384KB, linesize=64, ways=16, Inclusive=0)
L2 (size=512KB, linesize=64, ways=8, Inclusive=1)
L1d (size=32KB, linesize=64, ways=8, Inclusive=0)
PU#4 (cpuset: 0x00000010)
L3 (size=16384KB, linesize=64, ways=16, Inclusive=0)
L2 (size=512KB, linesize=64, ways=8, Inclusive=1)
L1d (size=32KB, linesize=64, ways=8, Inclusive=0)
PU#5 (cpuset: 0x00000020)
Core (cpuset: 0x000000c0)
L3 (size=16384KB, linesize=64, ways=16, Inclusive=0)
L2 (size=512KB, linesize=64, ways=8, Inclusive=1)
L1d (size=32KB, linesize=64, ways=8, Inclusive=0)
PU#6 (cpuset: 0x00000040)
L3 (size=16384KB, linesize=64, ways=16, Inclusive=0)
L2 (size=512KB, linesize=64, ways=8, Inclusive=1)
L1d (size=32KB, linesize=64, ways=8, Inclusive=0)
PU#7 (cpuset: 0x00000080)
Core (cpuset: 0x00000300)
L3 (size=16384KB, linesize=64, ways=16, Inclusive=0)
L2 (size=512KB, linesize=64, ways=8, Inclusive=1)
L1d (size=32KB, linesize=64, ways=8, Inclusive=0)
PU#8 (cpuset: 0x00000100)
L3 (size=16384KB, linesize=64, ways=16, Inclusive=0)
L2 (size=512KB, linesize=64, ways=8, Inclusive=1)
L1d (size=32KB, linesize=64, ways=8, Inclusive=0)
PU#9 (cpuset: 0x00000200)
Core (cpuset: 0x00000c00)
L3 (size=16384KB, linesize=64, ways=16, Inclusive=0)
L2 (size=512KB, linesize=64, ways=8, Inclusive=1)
L1d (size=32KB, linesize=64, ways=8, Inclusive=0)
PU#10 (cpuset: 0x00000400)
L3 (size=16384KB, linesize=64, ways=16, Inclusive=0)
L2 (size=512KB, linesize=64, ways=8, Inclusive=1)
L1d (size=32KB, linesize=64, ways=8, Inclusive=0)
PU#11 (cpuset: 0x00000800)
Prime95 64-bit version 29.5, RdtscTiming=1

just out of curiosity, what is wrong with the description? aside from the odd 12x16 MB L3. That would be a nice thing to have.

Prime95 · 2019-06-07, 08:22

Quote:

Originally Posted by Bigeagle

just out of curiosity, what is wrong with the description? aside from the odd 12x16 MB L3. That would be a nice thing to have.

Correct, hwloc is reporting far too many caches.

Prime95 · 2019-06-07, 18:53

Quote:

Originally Posted by Bigeagle

AMD Ryzen 5 2600 Six-Core Processor

just out of curiosity, what is wrong with the description? aside from the odd 12x16 MB L3. That would be a nice thing to have.

I opened a bug report with hwloc developers. They request the output of "coreinfo -cgnlsm".

Their initial guess is that version of the OS does not support this Ryzen well (yet).

ixfd64 · 2019-06-07, 20:20

Quote:

Originally Posted by Prime95

Also, I just tweaked the get-assignment server code for "what makes the most sense" prime95 clients.

Silly question: do newer versions still automatically get LL double-check assignments on new computers?

Bigeagle · 2019-06-08, 09:13

well, it's a win7 prof 64 bit, so a little suboptimal support is to be expected i guess

Code:

Coreinfo v3.31 - Dump information on system CPU and memory topology
Copyright (C) 2008-2014 Mark Russinovich
Sysinternals - www.sysinternals.com

Logical to Physical Processor Map:
**----------  Physical Processor 0 (Hyperthreaded)
--**--------  Physical Processor 1 (Hyperthreaded)
----**------  Physical Processor 2 (Hyperthreaded)
------**----  Physical Processor 3 (Hyperthreaded)
--------**--  Physical Processor 4 (Hyperthreaded)
----------**  Physical Processor 5 (Hyperthreaded)

Logical Processor to Socket Map:
************  Socket 0

Logical Processor to NUMA Node Map:
************  NUMA Node 0

No NUMA nodes.

Logical Processor to Cache Map:
*-----------  Data Cache          0, Level 1,   32 KB, Assoc   8, LineSize  64
*-----------  Instruction Cache   0, Level 1,   64 KB, Assoc   4, LineSize  64
*-----------  Unified Cache       0, Level 2,  512 KB, Assoc   8, LineSize  64
*-----------  Unified Cache       1, Level 3,   16 MB, Assoc  16, LineSize  64
-*----------  Data Cache          1, Level 1,   32 KB, Assoc   8, LineSize  64
-*----------  Instruction Cache   1, Level 1,   64 KB, Assoc   4, LineSize  64
-*----------  Unified Cache       2, Level 2,  512 KB, Assoc   8, LineSize  64
-*----------  Unified Cache       3, Level 3,   16 MB, Assoc  16, LineSize  64
--*---------  Data Cache          2, Level 1,   32 KB, Assoc   8, LineSize  64
--*---------  Instruction Cache   2, Level 1,   64 KB, Assoc   4, LineSize  64
--*---------  Unified Cache       4, Level 2,  512 KB, Assoc   8, LineSize  64
--*---------  Unified Cache       5, Level 3,   16 MB, Assoc  16, LineSize  64
---*--------  Data Cache          3, Level 1,   32 KB, Assoc   8, LineSize  64
---*--------  Instruction Cache   3, Level 1,   64 KB, Assoc   4, LineSize  64
---*--------  Unified Cache       6, Level 2,  512 KB, Assoc   8, LineSize  64
---*--------  Unified Cache       7, Level 3,   16 MB, Assoc  16, LineSize  64
----*-------  Data Cache          4, Level 1,   32 KB, Assoc   8, LineSize  64
----*-------  Instruction Cache   4, Level 1,   64 KB, Assoc   4, LineSize  64
----*-------  Unified Cache       8, Level 2,  512 KB, Assoc   8, LineSize  64
----*-------  Unified Cache       9, Level 3,   16 MB, Assoc  16, LineSize  64
-----*------  Data Cache          5, Level 1,   32 KB, Assoc   8, LineSize  64
-----*------  Instruction Cache   5, Level 1,   64 KB, Assoc   4, LineSize  64
-----*------  Unified Cache      10, Level 2,  512 KB, Assoc   8, LineSize  64
-----*------  Unified Cache      11, Level 3,   16 MB, Assoc  16, LineSize  64
------*-----  Data Cache          6, Level 1,   32 KB, Assoc   8, LineSize  64
------*-----  Instruction Cache   6, Level 1,   64 KB, Assoc   4, LineSize  64
------*-----  Unified Cache      12, Level 2,  512 KB, Assoc   8, LineSize  64
------*-----  Unified Cache      13, Level 3,   16 MB, Assoc  16, LineSize  64
-------*----  Data Cache          7, Level 1,   32 KB, Assoc   8, LineSize  64
-------*----  Instruction Cache   7, Level 1,   64 KB, Assoc   4, LineSize  64
-------*----  Unified Cache      14, Level 2,  512 KB, Assoc   8, LineSize  64
-------*----  Unified Cache      15, Level 3,   16 MB, Assoc  16, LineSize  64
--------*---  Data Cache          8, Level 1,   32 KB, Assoc   8, LineSize  64
--------*---  Instruction Cache   8, Level 1,   64 KB, Assoc   4, LineSize  64
--------*---  Unified Cache      16, Level 2,  512 KB, Assoc   8, LineSize  64
--------*---  Unified Cache      17, Level 3,   16 MB, Assoc  16, LineSize  64
---------*--  Data Cache          9, Level 1,   32 KB, Assoc   8, LineSize  64
---------*--  Instruction Cache   9, Level 1,   64 KB, Assoc   4, LineSize  64
---------*--  Unified Cache      18, Level 2,  512 KB, Assoc   8, LineSize  64
---------*--  Unified Cache      19, Level 3,   16 MB, Assoc  16, LineSize  64
----------*-  Data Cache         10, Level 1,   32 KB, Assoc   8, LineSize  64
----------*-  Instruction Cache  10, Level 1,   64 KB, Assoc   4, LineSize  64
----------*-  Unified Cache      20, Level 2,  512 KB, Assoc   8, LineSize  64
----------*-  Unified Cache      21, Level 3,   16 MB, Assoc  16, LineSize  64
-----------*  Data Cache         11, Level 1,   32 KB, Assoc   8, LineSize  64
-----------*  Instruction Cache  11, Level 1,   64 KB, Assoc   4, LineSize  64
-----------*  Unified Cache      22, Level 2,  512 KB, Assoc   8, LineSize  64
-----------*  Unified Cache      23, Level 3,   16 MB, Assoc  16, LineSize  64

Logical Processor to Group Map:
************  Group 0

Prime95 · 2019-06-08, 18:57

Quote:

Originally Posted by Bigeagle

well, it's a win7 prof 64 bit, so a little suboptimal support is to be expected i guess

From hwloc developers:

Quote:

coreinfo has the same bug, this likely confirms that the bug is in windows. You may want to update your windows since this processor is very recent.

Bigeagle · 2019-06-08, 19:58

thanks for your help :)
sadly updating is always a nasty thing since microsoft did some ... strange things to their update mechanism in win7 so it's always likely to fail without manual help and absolutely needs a full backup
i think i will try that if i got some time

probably the easiest thing concerning this (and other problems) would be to get a still supported OS, but linux is out of question on this machine (would be so easy ...) and win10 is uhm ... troublesome of it's own. at least in my personal opinion

let alone all that hassle with the updates there. sometime in the future when the owner is forced to drop win7 things will get very 'interesting' ^^
until then i'm happy if it works without too much problems since i'm the 'tech guy'

Similar Threads
Thread	Thread Starter	Forum	Replies	Last Post
Prime95 version 29.2	Prime95	Software	71	2017-09-16 16:55
Prime95 version 29.1	Prime95	Software	95	2017-08-22 22:46
Prime95 version 26.5	Prime95	Software	175	2011-04-04 22:35
Prime95 version 25.9	Prime95	Software	143	2010-01-05 22:53
Prime95 version 25.8	Prime95	Software	159	2009-09-21 16:30

2019-06-06, 13:10	#276
Bigeagle Jun 2019 2·3 Posts	Well, no. I did it now for the p95v298b3.win64.zip as the checksum is provided in the download section and it matches here - ftp://mersenne.org/gimps/ - i didn't find any checksums so i don't know how to check the older versions.

2019-06-06, 16:55	#278
Bigeagle Jun 2019 2·3 Posts	AMD Ryzen 5 2600 Six-Core Processor CPU speed: 3792.95 MHz, 6 hyperthreaded cores CPU features: 3DNow! Prefetch, SSE, SSE2, SSE4, AVX, AVX2, FMA L1 cache size: 12x32 KB, L2 cache size: 12x512 KB, L3 cache size: 12x16 MBL1 cache line size: 64 bytes L2 cache line size: 64 bytes Machine topology as determined by hwloc library: Machine#0 (total=28201712KB, Backend=Windows, hwlocVersion=2.0.3, ProcessName=prime95.exe) Package (total=28201712KB, CPUVendor=AuthenticAMD, CPUFamilyNumber=23, CPUModelNumber=8, CPUModel="AMD Ryzen 5 2600 Six-Core Processor ", CPUStepping=2) Core (cpuset: 0x00000003) L3 (size=16384KB, linesize=64, ways=16, Inclusive=0) L2 (size=512KB, linesize=64, ways=8, Inclusive=1) L1d (size=32KB, linesize=64, ways=8, Inclusive=0) PU#0 (cpuset: 0x00000001) L3 (size=16384KB, linesize=64, ways=16, Inclusive=0) L2 (size=512KB, linesize=64, ways=8, Inclusive=1) L1d (size=32KB, linesize=64, ways=8, Inclusive=0) PU#1 (cpuset: 0x00000002) Core (cpuset: 0x0000000c) L3 (size=16384KB, linesize=64, ways=16, Inclusive=0) L2 (size=512KB, linesize=64, ways=8, Inclusive=1) L1d (size=32KB, linesize=64, ways=8, Inclusive=0) PU#2 (cpuset: 0x00000004) L3 (size=16384KB, linesize=64, ways=16, Inclusive=0) L2 (size=512KB, linesize=64, ways=8, Inclusive=1) L1d (size=32KB, linesize=64, ways=8, Inclusive=0) PU#3 (cpuset: 0x00000008) Core (cpuset: 0x00000030) L3 (size=16384KB, linesize=64, ways=16, Inclusive=0) L2 (size=512KB, linesize=64, ways=8, Inclusive=1) L1d (size=32KB, linesize=64, ways=8, Inclusive=0) PU#4 (cpuset: 0x00000010) L3 (size=16384KB, linesize=64, ways=16, Inclusive=0) L2 (size=512KB, linesize=64, ways=8, Inclusive=1) L1d (size=32KB, linesize=64, ways=8, Inclusive=0) PU#5 (cpuset: 0x00000020) Core (cpuset: 0x000000c0) L3 (size=16384KB, linesize=64, ways=16, Inclusive=0) L2 (size=512KB, linesize=64, ways=8, Inclusive=1) L1d (size=32KB, linesize=64, ways=8, Inclusive=0) PU#6 (cpuset: 0x00000040) L3 (size=16384KB, linesize=64, ways=16, Inclusive=0) L2 (size=512KB, linesize=64, ways=8, Inclusive=1) L1d (size=32KB, linesize=64, ways=8, Inclusive=0) PU#7 (cpuset: 0x00000080) Core (cpuset: 0x00000300) L3 (size=16384KB, linesize=64, ways=16, Inclusive=0) L2 (size=512KB, linesize=64, ways=8, Inclusive=1) L1d (size=32KB, linesize=64, ways=8, Inclusive=0) PU#8 (cpuset: 0x00000100) L3 (size=16384KB, linesize=64, ways=16, Inclusive=0) L2 (size=512KB, linesize=64, ways=8, Inclusive=1) L1d (size=32KB, linesize=64, ways=8, Inclusive=0) PU#9 (cpuset: 0x00000200) Core (cpuset: 0x00000c00) L3 (size=16384KB, linesize=64, ways=16, Inclusive=0) L2 (size=512KB, linesize=64, ways=8, Inclusive=1) L1d (size=32KB, linesize=64, ways=8, Inclusive=0) PU#10 (cpuset: 0x00000400) L3 (size=16384KB, linesize=64, ways=16, Inclusive=0) L2 (size=512KB, linesize=64, ways=8, Inclusive=1) L1d (size=32KB, linesize=64, ways=8, Inclusive=0) PU#11 (cpuset: 0x00000800) Prime95 64-bit version 29.5, RdtscTiming=1 I assume this is what you meant.

2019-06-07, 07:38	#280
Bigeagle Jun 2019 2·3 Posts	The Workaround worked. I just get offered to run 24 workers by default :) AMD Ryzen 5 2600 Six-Core Processor CPU speed: 3473.40 MHz, 6 hyperthreaded cores CPU features: 3DNow! Prefetch, SSE, SSE2, SSE4, AVX, AVX2, FMA L1 cache size: 12x32 KB, L2 cache size: 12x512 KB, L3 cache size: 12x16 MBL1 cache line size: 64 bytes L2 cache line size: 64 bytes Machine topology as determined by hwloc library: Machine#0 (total=27862856KB, Backend=Windows, hwlocVersion=2.0.4rc1, ProcessName=prime95.exe) Package (total=27862856KB, CPUVendor=AuthenticAMD, CPUFamilyNumber=23, CPUModelNumber=8, CPUModel="AMD Ryzen 5 2600 Six-Core Processor ", CPUStepping=2) Core (cpuset: 0x00000003) L3 (size=16384KB, linesize=64, ways=16, Inclusive=0) L2 (size=512KB, linesize=64, ways=8, Inclusive=1) L1d (size=32KB, linesize=64, ways=8, Inclusive=0) PU#0 (cpuset: 0x00000001) L3 (size=16384KB, linesize=64, ways=16, Inclusive=0) L2 (size=512KB, linesize=64, ways=8, Inclusive=1) L1d (size=32KB, linesize=64, ways=8, Inclusive=0) PU#1 (cpuset: 0x00000002) Core (cpuset: 0x0000000c) L3 (size=16384KB, linesize=64, ways=16, Inclusive=0) L2 (size=512KB, linesize=64, ways=8, Inclusive=1) L1d (size=32KB, linesize=64, ways=8, Inclusive=0) PU#2 (cpuset: 0x00000004) L3 (size=16384KB, linesize=64, ways=16, Inclusive=0) L2 (size=512KB, linesize=64, ways=8, Inclusive=1) L1d (size=32KB, linesize=64, ways=8, Inclusive=0) PU#3 (cpuset: 0x00000008) Core (cpuset: 0x00000030) L3 (size=16384KB, linesize=64, ways=16, Inclusive=0) L2 (size=512KB, linesize=64, ways=8, Inclusive=1) L1d (size=32KB, linesize=64, ways=8, Inclusive=0) PU#4 (cpuset: 0x00000010) L3 (size=16384KB, linesize=64, ways=16, Inclusive=0) L2 (size=512KB, linesize=64, ways=8, Inclusive=1) L1d (size=32KB, linesize=64, ways=8, Inclusive=0) PU#5 (cpuset: 0x00000020) Core (cpuset: 0x000000c0) L3 (size=16384KB, linesize=64, ways=16, Inclusive=0) L2 (size=512KB, linesize=64, ways=8, Inclusive=1) L1d (size=32KB, linesize=64, ways=8, Inclusive=0) PU#6 (cpuset: 0x00000040) L3 (size=16384KB, linesize=64, ways=16, Inclusive=0) L2 (size=512KB, linesize=64, ways=8, Inclusive=1) L1d (size=32KB, linesize=64, ways=8, Inclusive=0) PU#7 (cpuset: 0x00000080) Core (cpuset: 0x00000300) L3 (size=16384KB, linesize=64, ways=16, Inclusive=0) L2 (size=512KB, linesize=64, ways=8, Inclusive=1) L1d (size=32KB, linesize=64, ways=8, Inclusive=0) PU#8 (cpuset: 0x00000100) L3 (size=16384KB, linesize=64, ways=16, Inclusive=0) L2 (size=512KB, linesize=64, ways=8, Inclusive=1) L1d (size=32KB, linesize=64, ways=8, Inclusive=0) PU#9 (cpuset: 0x00000200) Core (cpuset: 0x00000c00) L3 (size=16384KB, linesize=64, ways=16, Inclusive=0) L2 (size=512KB, linesize=64, ways=8, Inclusive=1) L1d (size=32KB, linesize=64, ways=8, Inclusive=0) PU#10 (cpuset: 0x00000400) L3 (size=16384KB, linesize=64, ways=16, Inclusive=0) L2 (size=512KB, linesize=64, ways=8, Inclusive=1) L1d (size=32KB, linesize=64, ways=8, Inclusive=0) PU#11 (cpuset: 0x00000800) Prime95 64-bit version 29.5, RdtscTiming=1 just out of curiosity, what is wrong with the description? aside from the odd 12x16 MB L3. That would be a nice thing to have.

2019-06-08, 19:58	#286
Bigeagle Jun 2019 6₈ Posts	thanks for your help :) sadly updating is always a nasty thing since microsoft did some ... strange things to their update mechanism in win7 so it's always likely to fail without manual help and absolutely needs a full backup i think i will try that if i got some time probably the easiest thing concerning this (and other problems) would be to get a still supported OS, but linux is out of question on this machine (would be so easy ...) and win10 is uhm ... troublesome of it's own. at least in my personal opinion let alone all that hassle with the updates there. sometime in the future when the owner is forced to drop win7 things will get very 'interesting' ^^ until then i'm happy if it works without too much problems since i'm the 'tech guy'