Cache and Memory Bandwidth Requirements for FFT

[LaurV]

As usual, a lot of blah-blah and false claims....

[axn]

Originally Posted by diep

Edit: at website of nvidia , there nvidia doesn't list its FP64 capaiblities yet at wikipedia i see it gets listed at not being lobotomized delivering 6.1 Tflops.
https://en.wikipedia.org/wiki/List_o...ocessing_units

That's confusing news then

Someone who happens to have one here ought to try to run some FP64 on it....

the 1.1 Tflops claim:

https://www.reddit.com/r/nvidia/comm...ision_monster/

See https://www.mersenne.ca/cudalucas.php for CuLu performance. Titan V is the fastest "consumer" grade card (only same generation Tesla/Quadro are faster).

[preda]

Originally Posted by diep

How do you want to do this?

Do you have C code to show this or pseudo-code of a working FFT that doesn't need this?

If you feel brave, feel free to peruse GpuOwl's implementation, which is extremely compact, the OpenCL part (the kernels) clocking in at only 1300 LOC in total: https://github.com/preda/gpuowl/blob/master/gpuowl.cl

It should be possible to do a 1:1 conversion to CUDA if desired. Or use as inspiration, or a starting point, only.

[nomead]

See https://docs.nvidia.com/cuda/turing-...ide/index.html

1.4.1.4. Integer Arithmetic
Similar to Volta, the Turing SM includes dedicated FP32 and INT32 cores. This enables simultaneous execution of FP32 and INT32 operations. Applications can interleave pointer arithmetic with floating-point computations. For example, each iteration of a pipelined loop could update addresses and load data for the next iteration while simultaneously processing the current iteration at full FP32 throughput.

Not talking about tensor cores now, that's just FP16 4x4 matrix multiply to an FP32 result matrix. Probably useless for our purposes, but who knows.

[diep]

Originally Posted by nomead

See https://docs.nvidia.com/cuda/turing-...ide/index.html

1.4.1.4. Integer Arithmetic
Similar to Volta, the Turing SM includes dedicated FP32 and INT32 cores. This enables simultaneous execution of FP32 and INT32 operations. Applications can interleave pointer arithmetic with floating-point computations. For example, each iteration of a pipelined loop could update addresses and load data for the next iteration while simultaneously processing the current iteration at full FP32 throughput.

Not talking about tensor cores now, that's just FP16 4x4 matrix multiply to an FP32 result matrix. Probably useless for our purposes, but who knows.

Those Tensor Cores deliver roughly against 100 Tflops performance - so for some clever sort of CRT based FP16 fft version there should be possibilities. 60-100 Tflops is really a lot.

The definition of 'executing at the same time' at a GPU is fuzzy logic because even generations of gpu's from 12 years ago and before basically take long time for an instruction to get out of the execution units - so there is a nonstop state of 'executing at the same time'. Furthermore if i run 8-20 warps of 32 cudacores at an 128 cudacore SIMD (9000 and 1000 series) or 192 cudacore SIMD (kepler) then obviously warps already get executed 'at the same time'. If the claim now is that if the same kernel with n warps has a mix of integer and floating point instructions and that you can get a higher IPC at a SIMD by mixing floating point and integer instructions through each other - that's implicitly more of the same.