mfaktc and PCIe bus width

[kracker]

Originally Posted by airsquirrels

Just find and replace CL_MEM_USE_HOST_PTR with CL_MEM_COPY_HOST_PTR in mfakto.cpp and gpusieve.cpp

Nice! I wasn't expecting much of an improvement at all for my GPU since it's not really bottlenecked, but I'm getting 387 GHz/days vs 380 Ghz/days now, it's better than nothing

[Mark Rose]

Did this change affect the performance of higher bit levels versus lower bit levels?

[Bdot]

You mean the fact that mfakto processes lower bitlevels faster? That is because mfakto needs to use different kernels (different implementations) for different bitlevels. This is unchanged. All kernels will benefit equally from this change (a certain percentage of improvement for each).

[Mark Rose]

Originally Posted by Bdot

You mean the fact that mfakto processes lower bitlevels faster? That is because mfakto needs to use different kernels (different implementations) for different bitlevels. This is unchanged. All kernels will benefit equally from this change (a certain percentage of improvement for each).

Yeah, that's what I was curious about. I was wondering if the kernels for higher bit levels were more memory intensive or not.