AMD Barton core - Page 2

xtreme2k · 2003-03-19, 22:09

256 doesnt help a whole lot but it does help. For what I know P4 cant even move 256 bit at the same time without using SSE2. Without SSE2 it wont be able to move more than 128 at the same time if what I remember is correct.

adpowers · 2003-03-20, 07:10

Here is a page comparing the cache improvements of a p4 to that of an athlon. http://www.anandtech.com/cpu/showdoc.html?i=1783&p=5

Also, I believe the reason Intel sued VIA was not because they had a DDR board, but because Intel didn't think VIA had the correct licenses. VIA, however, thought that since they acquired a company (or something) that owned the proper licenses, then they should be allowed to sell it. I don't remember exactly, but that is the gist of it.

nucleon · 2003-03-24, 12:43

Without researching and pulling this from where the sun doesn't shine: a 64bit path would require two read cycles from the L2 cache to read a double precision floating point number (80bit), 256bit path could read theoretically three double-fp in single read cycle. But I rekon it's more like two, and that would probably have to be with a packed data type. This is of course regardless of the L2 cache specifics. (cycles to check the tag, and cycles to transfer the data L2->registers.)

-- Craig

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2003-03-19, 22:09	#12
xtreme2k Aug 2002 174₁₀ Posts	256 doesnt help a whole lot but it does help. For what I know P4 cant even move 256 bit at the same time without using SSE2. Without SSE2 it wont be able to move more than 128 at the same time if what I remember is correct.

2003-03-20, 07:10	#13
adpowers Sep 2002 2⁴×5 Posts	Here is a page comparing the cache improvements of a p4 to that of an athlon. http://www.anandtech.com/cpu/showdoc.html?i=1783&p=5 Also, I believe the reason Intel sued VIA was not because they had a DDR board, but because Intel didn't think VIA had the correct licenses. VIA, however, thought that since they acquired a company (or something) that owned the proper licenses, then they should be allowed to sell it. I don't remember exactly, but that is the gist of it.

2003-03-24, 12:43	#14
nucleon Mar 2003 Melbourne 5×103 Posts	Without researching and pulling this from where the sun doesn't shine: a 64bit path would require two read cycles from the L2 cache to read a double precision floating point number (80bit), 256bit path could read theoretically three double-fp in single read cycle. But I rekon it's more like two, and that would probably have to be with a packed data type. This is of course regardless of the L2 cache specifics. (cycles to check the tag, and cycles to transfer the data L2->registers.) -- Craig