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Old 2011-02-22, 01:53   #89
Prime95
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Quote:
Originally Posted by James Heinrich View Post
Whereas 26.5.3 made no complaints, v26.5.4 now says (for an i7-920):Also, there's a typo "assigni" in undoc.txt (AffinityScramble2 section).
Set DebugAffinityScramble=1 in prime.txt and let me know what happens
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Old 2011-02-22, 01:59   #90
James Heinrich
 
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Quote:
Originally Posted by Prime95 View Post
Set DebugAffinityScramble=1 in prime.txt and let me know what happens
Code:
Mersenne number primality test program version 26.5
Optimizing for CPU architecture: Core i3/i5/i7, L2 cache size: 256 KB, L3 cache size: 8 MB
Test clocks: 95248
Logical CPU 1 clocks: 98237
Logical CPU 2 clocks: 95248
Logical CPU 3 clocks: 95248
Logical CPU 4 clocks: 95265
Logical CPU 5 clocks: 95283
Logical CPU 6 clocks: 95248
Logical CPU 7 clocks: 95248
Test clocks: 95248
Logical CPU 2 clocks: 95248
Logical CPU 3 clocks: 95248
Logical CPU 4 clocks: 95245
Logical CPU 5 clocks: 95248
Logical CPU 6 clocks: 95265
Logical CPU 7 clocks: 95248
Test clocks: 95265
Logical CPU 3 clocks: 182924
Test clocks: 95248
Logical CPU 5 clocks: 98163
Logical CPU 6 clocks: 95248
Logical CPU 7 clocks: 95248
Unable to detect some of the hyperthreaded logical CPUs.
See AffinityScramble2 in undoc.txt.
Starting workers.
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Old 2011-02-22, 02:29   #91
Prime95
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Interesting. You're in luck. Prime95's default is to assume logical 0,1 are one physical CPU, 2 and 3, 4 and 5, and 6 and 7. From your output, 2 and 3 clearly are one physical CPU. Thus you don't need to mess with AffinityScramble2.

My i7-860 is detected properly on Linux and Windows XP 64-bit. What's weird is that Linux numbers the logical CPUs differently than Windows.

v26.5b3 was not counting clocks properly on Windows. It was always getting a count of 0. When it tested the next logical processor, it also got a count of zero. Since that's twice as slow, it thought the two logicals made up one physical.

I don't know how to proceed. For now, I'll just gather more data unless a brainstorm hits me.

Last fiddled with by Prime95 on 2011-04-04 at 04:20
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Old 2011-02-22, 02:55   #92
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Running a benchmark seems to crash ("Illegal instruction") on the Linux 32-bit build. I recall seeing the crash in build 3 and 4; have not retested earlier builds, but I do know that the machine has run benchmarks before. Benchmark does work on Linux 64-bit and Windows 32-bit.

The machine in question is a dual PIII 1.4GHz, and it is using Slackware 13.1.

Let me know if you need additional information or for me to run with special settings on that machine.
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Old 2011-02-22, 03:24   #93
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Quote:
Originally Posted by KingKurly View Post
Running a benchmark seems to crash ("Illegal instruction") on the Linux 32-bit build.
Can you tell me the last text output prior to the seg fault?
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Old 2011-02-22, 05:45   #94
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Quote:
Originally Posted by Prime95 View Post
Can you tell me the last text output prior to the seg fault?
Sure, here it is. Let me know if there's anything else I can do.

Code:
kurly@slice:~$ mprime/mprime -m
[Main thread Feb 22 00:38] Mersenne number primality test program version 26.5
[Main thread Feb 22 00:38] Optimizing for CPU architecture: Pre-SSE2, L2 cache size: 512 KB
         Main Menu

     1.  Test/Primenet
     2.  Test/Worker threads
     3.  Test/Status
     4.  Test/Continue
     5.  Test/Exit
     6.  Advanced/Test
     7.  Advanced/Time
     8.  Advanced/P-1
     9.  Advanced/ECM
    10.  Advanced/Manual Communication
    11.  Advanced/Unreserve Exponent
    12.  Advanced/Quit Gimps
    13.  Options/CPU
    14.  Options/Preferences
    15.  Options/Torture Test
    16.  Options/Benchmark
    17.  Help/About
    18.  Help/About PrimeNet Server
Your choice: 16


Hit enter to continue: [Main thread Feb 22 00:38] Starting worker.
[Worker #1 Feb 22 00:38] Worker starting
[Worker #1 Feb 22 00:38] Your timings will be written to the results.txt file.
[Worker #1 Feb 22 00:38] Compare your results to other computers at http://www.mersenne.org/report_benchmarks
Illegal instruction
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Old 2011-02-22, 07:07   #95
Prime95
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Build 5 available. Fixes the dual-core non-SSE2 benchmark crash
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Old 2011-02-22, 10:17   #96
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I am trying to use the new build and register a new computer using the 26.5 version and all i am getting is the following

[Main thread Feb 22 10:03] Mersenne number primality test program version 26.5
[Main thread Feb 22 10:03] Optimizing for CPU architecture: Core i3/i5/i7, L2 cache size: 256 KB, L3 cache size: 3 MB
[Main thread Feb 22 10:03] Logical CPUs 0,1 form one physical CPU.
[Main thread Feb 22 10:03] Logical CPUs 2,3 form one physical CPU.
[Main thread Feb 22 10:04] Starting workers.
[Comm thread Feb 22 10:04] Updating computer information on the server
[Comm thread Feb 22 10:04] PrimeNet error 9: Access denied
[Comm thread Feb 22 10:04] Untrusted program versions currently excluded by PrimeNet
[Comm thread Feb 22 10:04] Visit http://mersenneforum.org for help.
[Comm thread Feb 22 10:04] Will try contacting server again in 70 minutes.

Has the new software been activated to work on the servers?
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Old 2011-02-22, 12:17   #97
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Hi George,

You had mentioned previously that for 26.5 you would update Prime95 to delete the P-1 save and backup files when they are finished being processed (or have a switch to do that). Was that complete?

The 26.5b3 client seems to be leaving them around still. Is there a switch I should be using or did you not have time to implement that?

Thanks,
Jeff.
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Old 2011-02-22, 16:10   #98
Prime95
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Quote:
Originally Posted by Jeff Gilchrist View Post
You had mentioned previously that for 26.5 you would update Prime95 to delete the P-1 save and backup files when they are finished being processed (or have a switch to do that). Was that complete?
undoc.txt, KeepPminus1SaveFiles.
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Old 2011-02-22, 16:16   #99
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Logical CPUs detection is clearly broken in b5, compared to b3 (I missed b4).
Using Core-i7 920 with Windows 7 x64:
Quote:
Optimizing for CPU architecture: Core i3/i5/i7, L2 cache size: 256 KB, L3 cache size: 8 MB
Unable to detect some of the hyperthreaded logical CPUs.
DebugAffinityScramble=1:
Quote:
Optimizing for CPU architecture: Core i3/i5/i7, L2 cache size: 256 KB, L3 cache size: 8 MB
Test clocks: 143255
Logical CPU 1 clocks: 147635
Logical CPU 2 clocks: 143280
Logical CPU 3 clocks: 142890
Logical CPU 4 clocks: 142890
Logical CPU 5 clocks: 142890
Logical CPU 6 clocks: 142890
Logical CPU 7 clocks: 142890
Test clocks: 144740
Logical CPU 2 clocks: 142965
Logical CPU 3 clocks: 142890
Logical CPU 4 clocks: 142890
Logical CPU 5 clocks: 142890
Logical CPU 6 clocks: 142890
Logical CPU 7 clocks: 142925
Test clocks: 142890
Logical CPU 3 clocks: 281945
Test clocks: 142890
Logical CPU 5 clocks: 275055
Unable to detect some of the hyperthreaded logical CPUs.
James Heinrich, I'd count this post as an addition to help George gather more data...

Last fiddled with by Commaster on 2011-02-22 at 17:11
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