View Single Post
Old 2013-11-22, 22:24   #6
fivemack
(loop (#_fork))
 
fivemack's Avatar
 
Feb 2006
Cambridge, England

11000111010112 Posts
Default

Quote:
Originally Posted by Aramis Wyler View Post
I don't have any good technical reasons to be concerned, but I get the impression that with quad channel memory you can't have more than one dimm per core, which was not the case with dual channel.
You can't have more than one DIMM per channel - every system will be like the cheaper X79 boards where there are precisely four memory slots and best performance requires populating all of them.

But the channels aren't attached to processor cores in a one-to-one way; the memory requests all go round the internal ring-bus and pick the channel that's attached to the memory module in which the cache line you're trying to act on is.

(Haswell-E is likely to have eight cores and four channels)
fivemack is offline   Reply With Quote