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Old 2009-02-21, 11:48   #11
ldesnogu's Avatar
Jan 2008

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Originally Posted by jasonp View Post
Anyone who is interested in these sorts of issues could look at some of the work of the F-CPU project, which is (was?) an attempt to design a general-purpose 64-bit CPU from scratch, with SIMD designed in from the ground up. Because the first implementations needed to be efficient on FPGAs, and these have a strict limit on the number of read and write ports to the logic you would use for register files, the instruction set has many instructions that write two registers (e.g. a sum and a carry out in register (X) and (X XOR 1), respectively).
It looks like F-CPU has been dead for years. The fact they had instructions that could write 2 registers is eased by the fact they only committed one instruction per cycle Another open project, OpenRISC, seemingly only has one output per instruction.

Section 5.1 of the book Embedded Computing: A Vliw Approach To Architecture, Compilers And Tools explains that the area of a register file increases as the square of the number of ports and access time increases linearly with the number of ports. Section 5.4.2 also explains how large the forwarding network can grow.

Anyway that doesn't explain why x86 SIMD various instruction sets are so odd. I guess it's the result of adding a few instructions at each generation, instead of spending a few years in R&D thinking about what is really needed in the longer term.
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