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Old 2002-08-23, 18:30   #35
ebx
 
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Aug 2002

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Well, XP and P4 can both do prefetch. If the code is optimalized that way for the critical path, you will always have your data in cache when you need it. Prefetching gave me 30% boost when I implemented it for a work project. It may even be better for todays P4/XP since their frequency is a lot higher and memory access speed still in the same order. 2G CPU clocked at 0.5ns and 133FSB memory cycle is (I am guestimating) still at over 10ns. (Hey, maybe I can do that for prime95 and claim a slice of the EFF prize. :D ) You dont know how your bus is utilized until you put it under a logic analyzor. Besides, all the memory access are bursted meaning you get a whole cache line in even if you only need a byte from it. If your data access folllows the locality anticipated, by bursting your next data is in cache now. XP has a 64 byte L2 cacheline. That further reduce the latency effect of async buses.

I didnt read kt333 spec. Dont know if data is buffered. I admitted for the chips I worked with, they were all sync.

Angular, I will sent you a PM for the vendor. It is not a big vendor. Boxes from big vendors can never be performance king. They may offer low cost and good services for volume buyers. But never performance in our sense.
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