Thread: Apple M1 SoC
View Single Post
Old 2020-11-12, 23:32   #4
Ethan (EO)
 
Ethan (EO)'s Avatar
 
"Ethan O'Connor"
Oct 2002
GIMPS since Jan 1996

22×23 Posts
Default

Anandtech ran spec2006 on an A14 - the mobile platform CPU/SOC believed to be the basis for the M1 - and it almost equals a Ryzen 9 5950x but only needs a 5W power envelope to do it, including DRAM:

https://images.anandtech.com/graphs/...226/111168.png


The M1 should be even faster.

The A14 has huge, fast L1 - 192kb L1I and 128kb L1D per big core, with 3 cycle latency on the L1D - and a unified 16MB L2 with 16 cycle latency, shared across the CPU, GPU, and accelerators. The memory space is unified across the whole platform, and the DRAM is in-package with the CPU, although it is LPDDR4x, not HBM.

Other stats are also bleeding edge - 600+ entry reorder buffer, 350+ register rename capacity, at least 7 integer, 4 L/S, and 4 FPU/SIMD execute slots, the last of which each execute 1 FMUL and 1 FADD per cycle with 4 and 3 cycle latency respectively.

(all from https://www.anandtech.com/show/16226...14-deep-dive/2)

Things should get very interesting once they start making Mx chips with faster, bigger ram and desktop power and thermals.
Ethan (EO) is offline   Reply With Quote