At one time DC got done within the hardware lifetime of the system that did the first test.
Flaky systems got identified and corrective action could be taken regarding all their output in a timely manner (early triple check), and also the user could be notified their still-producing system was unreliable and any hardware issues addressed and output reliability improved.
Over the past 20 years, the gap between first test and double check has grown drastically, from under two years, to nearly a decade, longer than typical hardware lifetime.
Recent trends are toward more primality testing, less DC, so the gap will worsen (is worsening).
I think the required DC rate should be increased to get this large and growing lag under control.
Method used to gauge gap was to view a 1000-range of exponent beginning at the indicated base value, and find the longest time gap within that sample interval. For example,
https://www.mersenne.org/report_expo...0001000&full=1
Code:
base LL year DC time gap years
3M (most date data missing)
4M 1998 1.5 (some first-test dates missing)
5M 1998 2.2
10M 2000 3.7
20M (first-test dates missing)
30M 2005 6.9
40M 2007 9.2 (some first-test dates missing)
50M 2010 8.6
60M 2013 6.9/tbd
70M 2011 8.2/tbd
80M 2011 6.3/tbd
90M 2017 3.0/tbd
100M 2013 7.7/tbd
>100M tbd
(Note, a less detailed version of this was initially posted as
https://www.mersenneforum.org/showpo...postcount=4621)
The development of a proof method for PRP with independent certification is reducing the addition of new DC backlog and speeding checking of PRP results. The transition to PRP with proof generation will allow eventual completion of the LLDC backlog. (Mprime or prime95 30.2 or later, gpuowl 6.11-310 or later have PRP proof generation capability; Mlucas capability is in development.)
Top of this reference thread:
https://www.mersenneforum.org/showthread.php?t=23845
Top of reference tree:
https://www.mersenneforum.org/showpo...22&postcount=1