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-   -   Which type of RAM is faster? (https://www.mersenneforum.org/showthread.php?t=30)

Angular 2002-08-23 18:27

[quote="xtreme2k"]If what you are refering to is correct. A mobo will have to have a 256 bit memory interface to the chipset, which doesnt exist for for now. [/quote]

If you do not believe [url=http://www.supermicro.com]SuperMicro[/url], then read ServerWorks's own web page [url]http://www.rccorp.com/products/matrix.html[/url]. Refer to GC HE Column. It does have a 256 bit memory interface.

diep 2023-01-01 14:21

[QUOTE=jeff8765;650]Which type of RAM is faster for GIMPS the RDRAM or the DDR RAM?

EDIT: Added question mark.[/QUOTE]

The answer is not so simple to answer because it depends upon the job and need to take into account also cache usage.

It is all 1 big bandwidth problem. Yet there is special trick that messes up bandwidth problem.

If the answer is just getting from random spot couple of bytes - then the answer might surprise you.
DDR3 for example can quickly deliver 32 bytes and then abort the rest of the cacheline of 64 bytes.

Yet in general spoken: more memory channels is better. However there is also a limit there and weird things.

For example one might guess 4 channels DDR4 with Intel Xeon cpu i've got here 2699v4 (sure i have ES versions here was much cheaper some time ago). Yet many chinese local market (local in china) cheap motherboards from like 50 dollar a piece, they have 2 channels on paper. However they use trick that 2 dimms cooperate somehow. So performance in reality is close to 4 channels.

4x bandwidth of a single DIMM is of course nice to have.

One would guess then some more highend chip there that can have 4 channels + 2 dimms cooperating, effectively that's similar to nearly 8 channels - yet officially it's 4 channels. One would guess that this is magnificent better. Problem is that the maximum bandwidth the CPU can handle is just 10% above 4 channels. So the additional 4 dimms delivering in theory factor 2 more bandwidth then do not help.

So what you seek is memory banwidth x number_of_channels x dimms_cooperating >= bandwidth cpu can handle.

Then there is of course REG ECC memory - we gladly pay the price for the extra clock that registered memory eats over unbuffered.

Now for GPU's there is another problem that was there some years ago. GDDR5 itself already has a CRC to check validity of the data. Yet for sysadmins it's not such easy to use feature. ECC on other hand means huge problems for hardware designers to add to a chip. We all like to have it - yet it's a big burden on performance of the system.

So in short non-ecc unbuffered memory is always going to be faster. Yet i would never accept anything else than ECC for a HPC system that government might build. There is a paper reality on how research might be done and there is practice. practice is that 99% of researchers is not so clever like me and not so critical at results they spit out. Showing a result outweighs anything else. In short any calculation they do the hardware conditions such as ECC should be there to avoid such sort of error from happening. Yet it's a big performance burden and huge extra price.

diep 2023-01-01 14:26

Auch - this was reply upon posting from 21 years ago :)

PhilF 2023-01-01 17:06

Better late than never, I always say. :smile:

retina 2023-01-01 17:19

The answer was given in post #3. Responses after that can be safely ignored.


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