[QUOTE=diep;621794]In your dreams - with such low power 8 core chiplets they may be happy with above 80% i would guess. Really happy.

We'll never know what their yield is. Figuring out all secrets of the B2 bomber is much easier than that. Heh didn't USA crash such a drone version of the B2 in 2011 completely intact in Iran? Yeah yields is one of the REAL secrets on this planet!

Yet rule of thumb is that a yield over 80% is needed to make a good profit on CPU's. Now this is far more expensive cpu's so throw some dices to gamble the real yield value.

If yield was really brilliant they would have flooded the market with 64 core cpu's and for years there was a shortage.

Tells me it's difficult to get good yields with it and probably it gets produced in the center of a wafer. The rest of the wafer having other cpu's.

So in dead center of the wafer where the machine produces the best results, they have problems getting to 80% yield is my blindfolded guess.[/quote]

I should have said effective 99% yields, because even if given chiplet is highly defective, there is a place in the product stack it can be used. Only very unfortunate defects will hit a chiplet in a critical spot.

Use a defect density calculator like [url]https://isine.com/resources/die-yield-calculator/[/url]

A Zen 4 chiplet is 70 mm^2. I don't have exact dimensions, but call it 7 x 10. TSMC has a defect rate of about 0.07/cm^2. Edge loss of 3 mm, and 0.2 mm scribe lines, 300 mm wafer.

You get a 95% yield of defect-free dies.

Of the 5% that do have defects, most defects will occur in a core or in L3 cache. If the L3 is hit, fuse off half and sell the die in an Epyc 9224. Or like a future Zen 4 Ryzen like the Ryzen 3 5500. If a core is defective, sell it as a chiplet with fewer than 8 cores active.

Dies farther from the center are likely to need more power or to clock lower, yes. Sell those as desktop chips, the least power sensitive market. The best go in high core count Epycs.

So yeah, 99% effective yields are easily attained on the chiplets.

As the IO dies are much bigger yields will be lower there.

AMD didn't flood the market with 64 core chips because there was limited capacity at TSMC until very recently.

With yields i mean chips that get out of the wafer that you do not need to shredder right away even before it gets tested nonstop for a week or more which cores could work and if so at which common Ghz clock the chip can run if any at all.

I doubt AMD is above 80% and if they are - very little. Maybe 80.1% even - after all those years.
Look how bad those cpu's are available for years now.

We speak about the latest ASML machines made here in Netherlands that are located in Taiwan at TSMC that they produce this with. It's a huge accomplishment they managed.

Then each so time they guess they have a new tweak to get up yields, they move the software upgrade from Netherlands to Taiwan - an airplane with a few guys will arrive in Taiwan - incorporate it and travel back after upgrade done.

Takes years and years to get such new factory to work at a yield rate that is acceptable anyhow.

I read somewhere a chiplet is 112+mm^2 but could've been talking about something totally different.

Remember that there is a crossbar that has to serve a huge bandwidth and low latency for any sort of cache coherency protocols that are there.

You can throw your defect rate completely out of the window at a new process. Center of the wafer or edge of the wafer - difference couldn't be larger there. Possibly producing low clocked memory chips at the edges of every wafer.

Someone who taped out a certain huge chip for AMD some time ago told me the next rule of thumb. They start at 300Mhz and from there on they need to fix the chips design to run at the Ghz level it gets sold at. And only after that improve yields as well.

Remember this is a technology so finegrained - no one else on the planet is able to produce cpu's with it. Getting the kinks out of that is much harder than building a space shuttle.

[QUOTE=Mark Rose;621807]I should have said effective 99% yields, because even if given chiplet is highly defective, there is a place in the product stack it can be used. Only very unfortunate defects will hit a chiplet in a critical spot.

Use a defect density calculator like [url]https://isine.com/resources/die-yield-calculator/[/url]

A Zen 4 chiplet is 70 mm^2. I don't have exact dimensions, but call it 7 x 10. TSMC has a defect rate of about 0.07/cm^2. Edge loss of 3 mm, and 0.2 mm scribe lines, 300 mm wafer.

You get a 95% yield of defect-free dies.

Of the 5% that do have defects, most defects will occur in a core or in L3 cache. If the L3 is hit, fuse off half and sell the die in an Epyc 9224. Or like a future Zen 4 Ryzen like the Ryzen 3 5500. If a core is defective, sell it as a chiplet with fewer than 8 cores active.

Dies farther from the center are likely to need more power or to clock lower, yes. Sell those as desktop chips, the least power sensitive market. The best go in high core count Epycs.

So yeah, 99% effective yields are easily attained on the chiplets.

As the IO dies are much bigger yields will be lower there.

AMD didn't flood the market with 64 core chips because there was limited capacity at TSMC until very recently.[/QUOTE]

[QUOTE=Mark Rose;621807] AMD didn't flood the market with 64 core chips because there was limited capacity at TSMC until very recently.[/QUOTE]

Limited capacity for a chip they can make so much money with and push Intel out of the market with only occurs when yield is too low. Zero other explanations possible. The big moneymaker also will continue production during covid or whatever other problems. I'm not aware exactly what the amount of cash that was quoted yet we can think of order of 20 billion dollar invested in such production facility at this proces. In short the machines have to nonstop generate product to pay back that 20 billion dollar otherwise TSMC is bankrupt. So whatever you produce - yields have to be good otherwise that design needs nonstop fixes while producing very little meanwhile other products that make more cash have a priority.

The yields were not good enough yet in short. Better produce something massively later if yields are not good and do minimum production now in order to bugfix the chips yields and as they call it 'cream off the market' in old school macro-economics. Too many dozens of billions are on stake.

Yields yields yields!

Note that the L3 cache from a distance seen you can see it as a piece of SRAM that's on-chip.

[QUOTE=diep;621812]Limited capacity for a chip they can make so much money with and push Intel out of the market with only occurs when yield is too low. Zero other explanations possible.
...[/QUOTE]

They're fabless and until a few years ago were dragging themselves out of bankruptcy and extricating themselves from global foundries contracts that were in place as a result of going fabless. Market forces on TSMC's highly sought-after nodes, and probably limited-until-recently ability to bid/acquire as much allocation as perhaps hindsight shows they should have, are definitely factors.