RISC-V
 

[URL]https://www.techpowerup.com/274024/risc-v-comes-to-pc-sifive-introduces-hifive-unmatched-development-board[/URL]

[URL]https://www.sifive.com/boards/hifive-unmatched[/URL]



[URL]https://en.wikipedia.org/wiki/RISC-V[/URL]
[QUOTE]Unlike most other ISA designs, the RISC-V ISA is provided under open source licenses that do not require fees to use.[/QUOTE]:mike:

It's a good step, but RISC-V is still many years from being viable in a consumer chip. That board is for evaluation and jumpstarting dev efforts and is still a few orders of magnitude off price-wise. No one's stepped up and mass-produced a design for consumer adoption yet, that may not be realistic anytime soon because the majority of consumers require an iGPU and unless I'm out of the loop that looks to be a bit of a problem.

I was looking at that yesterday, and it's nice they finally have a useful desktop board. It would be fun to run that as a novelty.

[youtube]HVsnnYuvDXI[/youtube]

[QUOTE=Xyzzy;561541][URL]https://www.techpowerup.com/274024/risc-v-comes-to-pc-sifive-introduces-hifive-unmatched-development-board[/URL]

[URL]https://www.sifive.com/boards/hifive-unmatched[/URL]



[URL]https://en.wikipedia.org/wiki/RISC-V[/URL]
:mike:[/QUOTE][borat]Very nice[/borat]

[url]https://www.mouser.com/new/sifive/sifive-hifive/[/url]

[QUOTE=Xyzzy;562704][url]https://www.mouser.com/new/sifive/sifive-hifive/[/url][/QUOTE]

At £515.31 what is the advantage of this board other than openness?

I have ordered a Sipeed Longan Nano RISC-V GD32VF103CBT6 for £6.70 in order to play with the RISC-V instruction set. It supports RV32IMAC instruction set.

[QUOTE=paulunderwood;562706]At £515.31 what is the advantage of this board other than openness?[/QUOTE]It looks like fun!

Other kinda-related news: [URL]https://riscv.org/blog/2020/11/picorio-the-raspberry-pi-like-small-board-computer-for-risc-v/[/URL]

[QUOTE=paulunderwood;562706]
I have ordered a Sipeed Longan Nano RISC-V GD32VF103CBT6 for £6.70 in order to play with the RISC-V instruction set. It supports RV32IMAC instruction set.[/QUOTE]

Ahead or the delivery of my Sipeed Longan Nano, I have started programming a RISC-V assembly code library for arbitrary precision arithmetic as a basis of doing some speudoprimaility tests. I have written array_add and array_mul so far -- though I need the device for debugging purposes.

The tools I am using are Visual Studio Code with the PlatformIO plug-in which deals with uploads to the Longan Nano.

I found some easy to follow learning material on the net, including YouTube,

My Longan Nano arrived today. Now I can start debugging my arbitrary arithmetic code. I have a RISC-V book on order -- the one with a picture of Mona Lisa on the front.

Edit: I now need a usb-c cable. Also for another £3 I could have got a LCD display and a case :down:

[QUOTE=paulunderwood;564094]My Longan Nano arrived today. Now I can start debugging my arbitrary arithmetic code. I have a RISC-V book on order -- the one with a picture of Mona Lisa on the front.

Edit: I now need a usb-c cable. Also for another £3 I could have got a LCD display and a case :down:[/QUOTE]
Ha! That board is just a $3-$4 "-ino" board, many vendors have. We use similar toys [URL="https://www.google.com/search?client=firefox-b-d&q=stm32+nucleo+32"]from STM[/URL] in our daily job. You can PM us your address and we can send you few. Don't expect a lot of performance, haha, I mean I know that Risc-V is about 10% to 15% "innate" faster than Cortex-M (i.e. clock per clock), and that the core consumption in run mode could be about a half, to a third, of a Cortex-M core, depending on what you do with it, but the peripherals (timers, etc) inside are the same, and at the end, this is just a board running at 48MHz or so, so you can't do much with it. Next step would be to put together 960 of them and give them TF work (in such a way, for a given p and bitlevel, each will work a single class of k's from the 960 classes). They will consume about 30 mW per chip, which is about 28 Watt, and if you make 10 such contraptions, you will get the performance of an average-to-high-end GPU, for the same power consumption. Except, this will cost you to build (at ~$0.6 per chip if you buy large qty) about $6000. :razz:

Thanks for the offer, but I want to concentrate on RISC-V for now -- that is complicated enough! I like the way every thing is open, with architecture diagrams etc. I will be reading my RISC-V book and debugging my code when the usb-c cable arrives.

I ordered another Longan Nano, this time making sure it came with the screen and case! I spent many hours trying to get something to work -- so I can run my aribitrary arithmetic development programs. I found this [URL="https://sigmdel.ca/michel/ha/gd32v/longan_nano_01_en.html"]excellent page[/URL] that has a download which when unzipped in the right place ran the screen in all its techocolour. I was then on a position to start hacking. This is not by running a debugger but making a changes and testing for the expected results on the screen. Oh what fun! :truck:

[url]https://arstechnica.com/gadgets/2021/01/seeed-and-beagleboard-team-up-to-provide-a-new-risc-v-based-linux-pc/[/url]

[QUOTE=Xyzzy;569199][url]https://arstechnica.com/gadgets/2021/01/seeed-and-beagleboard-team-up-to-provide-a-new-risc-v-based-linux-pc/[/url][/QUOTE]

Can you tell me whether the BeagleV will be 32 bit or 64 bit?

Edit; according to [url]https://www.tomshardware.com/news/beaglev-riscv-announced[/url] it had a dual core 64 bit U74 CPU.

GMP's Torbjörn Granlund weighs in on RISC-V, and does not mince words:
[quote]Date: Mon, 20 Sep 2021 11:53:13 +0200
From: Torbjörn Granlund <tg@gmplib.org>
To: [email]gmp-devel@gmplib.org[/email]
Subject: Risc V greatly underperforms
Message-ID: <86bl4nefp2.fsf@shell.gmplib.org>
Content-Type: text/plain; charset=utf-8

It seems safe to assume that most people on this list have heard of
Risc V by now, the license-free instruction set.

I trust that much fewer have looked at the technical details. I have,
though, as we implement critical inner loops for GMP in assembly.

My conclusion is that Risc V is a terrible architecture. It has a
uniquely weak instruction set. Any task will require more Risc V
instructions that any contemporary instruction set. Sure, it is
"clean" but just to make it clean, there was no reason to be naive.

I believe that an average computer science student could come up with
a better instruction set that Risc V in a single term project. It is,
more-or-less a watered down version of the 30 year old Alpha ISA after
all. (Alpha made sense at its time, with the transistor budget
available at the time.)

Let's look at some examples of how Risc V underperforms. First,
addition of a double-word integer with carry-out:
[code]
add t0, a4, a6 // add low words
sltu t6, t0, a4 // compute carry-out from low add
add t1, a5, a7 // add hi words
sltu t2, t1, a5 // compute carry-out from high add
add t4, t1, t6 // add carry to low result
sltu t3, t4, t1 // compute carry out from the carry add
add t6, t2, t3 // combine carries
[/code]
Same for 64-bit arm:
[code]
adds x12, x6, x10
adcs x13, x7, x11
[/code]
Same for 64-bit x86:
[code]
add %r8, %rax
adc %r9, %rdx
[/code]
(Some additional move insn might be needed for x86 due to the
2-operand nature of this arch.)

If we generalise this to GMP's arbitrarily wide addition, we will end
of with 2 to 3 times more instructions, and go from just over 1 cycle
per 64-bit result word to 3 cycles per word. The 3 cycles will happen
even for a wide implementation which could execute a large number of
instructions in parallel. The critical path will be add->sltu->add
which are three dependent instructions i.e. 3 cycles.

I have heard that Risc V proponents say that these problems are known
and could be fixed by having the hardware fuse dependent instructions.
Perhaps that could lessen the instruction set shortcomings, but will
it fix the 3x worse performance for cases like the one outlined here?
Why not provide a decent instruction set instead?

I don't think designing a decent ISA is terribly difficult. Designing
a great ISA is. Designing something like that Risc V is trivial.

Full disclosure: I have no financial or other interest in any computer
architecture mentioned here or not mentioned here. I really like the
idea of a license-free ISA.

--
Torbjörn
Please encrypt, key id 0xC8601622[/quote]

[QUOTE=ewmayer;589572]GMP's Torbjörn Granlund weighs in on RISC-V, and does not mince words:[/QUOTE]Performance is just one dimension to consider for any CPU.

Consider the PIC16 instruction set. Performance-wise it is terrible. But the CPUs implementing it sell in large numbers. Clearly not many people buying those care much about the performance. Or if they do then they are in for a nasty shock.

If my FPGA is small then perhaps RISC-V will be a perfect choice for a small low power controller device.

Does the relatively high number of registers (32 integer and 32 float registers is high right?) have a positive impact to compute-heavy operations?



[QUOTE=ewmayer;589572]GMP's Torbjörn Granlund weighs in on RISC-V, and does not mince words:[/QUOTE]
I don't doubt they know what they're talking about, but having instructions for low and high words seems strange. If I'm interpreting it right they're saying that 64 bit addition on a 64bit Risc-V chip (that uses RV64I) does the operations with 32 bit integers?

[QUOTE=M344587487;589612]Does the relatively high number of registers (32 integer and 32 float registers is high right?) have a positive impact to compute-heavy operations?

I don't doubt they know what they're talking about, but having instructions for low and high words seems strange. If I'm interpreting it right they're saying that 64 bit addition on a 64bit Risc-V chip (that uses RV64I) does the operations with 32 bit integers?[/QUOTE]

Not all the registers are general purpose -- some seem to be for I/O.

I like the small set of registers and instructions. They are easy to remember and therefore to program. Oh what fun! Takes me back to the days when I did assembly for the Zilog Z80

RISC-V comes in many flavours -- 32/64 bit, single/multi core, with or without multiplication etc -- It is an open ISA leaving it to hardware implementors to choose what they include.

[QUOTE=M344587487;589612]but having instructions for low and high words seems strange.[/QUOTE]
[quote]First, addition of a double-word integer with carry-out:[/quote]

He's just giving the example of the simplest case of a multi-word addition, i.e. two words. As can be seen from equivalent ARM & x64, this is the addition of two 2x64 integers.

[QUOTE=axn;589618]He's just giving the example of the simplest case of a multi-word addition, i.e. two words. As can be seen from equivalent ARM & x64, this is the addition of two 2x64 integers.[/QUOTE]Thanks it makes sense now, what threw me is that the 64 bit base is defined in the riscv manual relative to the 32 bit base but there's no explicit redefinition of a word now being 64 bit (which should have been obvious), so I interpreted the example completely wrong. So the problem boils down to risc-v not having a carry bit which means there is no add-taking-into-account-previous-carry op, that is an issue.

I've met this issue programming in assembly language on a s/370-XA. But that design dates from the 1960s which is a partial explanation (it doesn't even have a stack!) There's no excuse for any IS designed after 1980 not to have a carry bit (unless a very cut down system where low power/cost override everything else).

Even a 8080 or a 6502 had a carry bit.

FWIW (not much) I implemented a base 3 Fermat PRP multi-limb test on my 32 bit Longan Nano. With a 16 bit model, a mult fits in in 32 bits with room for two 16 bit additions without overflow. I do sympathize with the GMP developers about the lack of instructions, but this is RISC and it is open and fun!

[URL]https://riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf[/URL]
[quote]We did not include special instruction set support for overflow checks on integer arithmetic
operations in the base instruction set, as many overflow checks can be cheaply implemented using
RISC-V branches. Overflow checking for unsigned addition requires only a single additional
branch instruction after the addition: add t0, t1, t2; bltu t0, t1, overflow.
For signed addition, if one operand’s sign is known, overflow checking requires only a single
branch after the addition: addi t0, t1, +imm; blt t0, t1, overflow. This covers the
common case of addition with an immediate operand.
For general signed addition, three additional instructions after the addition are required,
leveraging the observation that the sum should be less than one of the operands if and only if the
other operand is negative.
add t0, t1, t2
slti t3, t2, 0
slt t4, t0, t1
bne t3, t4, overflow[/quote]Oh dear. I wonder how many designers have contemplated an extension that adds an a=a+b instruction that uses the spare register as a carry flag (if arbitrary operand modification is even possible) (if limiting to three operands is as desirable as it appears to be).

Attached is a "src" zip for the Longan Nano.

I plan to combine the assembly code into one big function. Anyone willing to look a the assembly code and make recommendations for improvement will be praised.

Here is main.cpp:

[CODE]
/*
Performs the test (x+2)^(n+1)==5 mod(n,x^2+1) for n==3 mod 4.
32 bit numbers only using 2x array of 32 bits.
*/

#include <Arduino.h>

typedef unsigned int num[2];

extern "C" {
#include "lcd/lcd.h"
extern void from32to16(num *r, unsigned int *a);
extern void from16to32(unsigned int *r, num *a);
extern void getPartial(unsigned int *r, unsigned int *a);
extern void getBigNum(num *r, unsigned int *a);
extern void setMask(unsigned int *r, unsigned int *a);
extern void mulit(num *r, num *a, num *b, num *npar);
extern void addit(num *r, num *a, num *b, num *nbig);
extern void negit(num *r, num *a, num *nbig, num *npar);
extern void cpy(num *r, num *a);
extern void shr(unsigned int *a);
extern int prp(unsigned int *n);
}

void setup() {
Lcd_Init();
LCD_Clear(BLACK);
}

unsigned int n=7;
unsigned int np1, mask, nbigInt, nparInt, S, T;
num s, t, tmp1, tmp2, tmp3, ndw, npar, nbig;
char buf[80];

void loop() {
getBigNum(&nbig, &n);
getPartial(&nparInt, &n);
from32to16(&npar, &nparInt);
s[1]=0;s[0]=1;
t[1]=0;t[0]=2;
np1=n+1;
setMask(&mask, &np1);
while (mask) {
mulit(&tmp2, &s, &t, &npar);
addit(&tmp1, &tmp2, &tmp2, &npar);
negit(&tmp3, &s, &nbig, &npar);
addit(&tmp2, &tmp3, &t, &npar);
addit(&tmp3, &s, &t, &npar);
mulit(&t, &tmp2, &tmp3, &npar);
cpy(&s, &tmp1);
if(np1&mask){
addit(&tmp2, &s, &s, &npar);
addit(&tmp1, &tmp2, &t, &npar);
addit(&tmp3, &t, &t, &npar);
negit(&tmp2, &s, &nbig, &npar);
addit(&t, &tmp3, &tmp2, &npar);
cpy(&s, &tmp1);
}
mask=(mask>>1); //shr(&mask);
}
from16to32(&S, &s);
from16to32(&T, &t);
S%=n;
T%=n;
if(S==0&&T==5) {
sprintf(buf, "%u Is prime!", n);
LCD_ShowString(10, 20, (u8 const *) buf, GREEN);
} else {
sprintf(buf, "%u composite", n);
LCD_ShowString(10, 20, (u8 const *) buf, RED);
}
if (n==4294967291) return;
n+=4;
delay(1000);
}
[/CODE]

There is now [URL="https://mangopi.org/mangopi_mqpro"]Mango Pi MQ Pro[/URL] which is a single 64-bit RISC-V SoC (system on a chip) board with mini hdmi and usb-c outputs, wifi and bluetooth. Early doors, yet will just about run a light weight desktop environment.

Cheap on AliExpress but at rip off price on eBay.