Skylake AVX-512
 

Will Prime95 benefit greatly from the AVX-512 in the coming in 2015 Skylake processors?

Yes and no.

The extra registers will be very useful. The wider registers if backed up by wider execution units would double peak FP throughput. However, prime95 is currently bandwidth limited. Unless Skylake has quad channel memory gains will be very limited.

[QUOTE=Prime95;389530]Yes and no.

The extra registers will be very useful. The wider registers if backed up by wider execution units would double peak FP throughput. However, prime95 is currently bandwidth limited. Unless Skylake has quad channel memory gains will be very limited.[/QUOTE]
Skylake will support DDR4.

My understanding is DDR4 does not imply quad channel

[QUOTE=Prime95;389530]Yes and no.

The extra registers will be very useful. The wider registers if backed up by wider execution units would double peak FP throughput. However, prime95 is currently bandwidth limited. Unless Skylake has quad channel memory gains will be very limited.[/QUOTE]

Are you saying that in a perfect world of infinite memory bandwidth, Skylake might see a double in total speed? Or is that gain just in one step of the process?


Also, I've been meaning to ask about the data that Prime95 actually needs. I think you've said before that there's a bunch of sine and cosine data that takes up a bunch of space. Is that for the FFT? Can two workers share the same data if their FFT size is the same?

[QUOTE=kracker;389531]Skylake will support DDR4.[/QUOTE]

[QUOTE=Prime95;389532]My understanding is DDR4 does not imply quad channel[/QUOTE]

I'm also doubtful of seeing Quad channel on Skylake. We've never seen anything past dual-channel on the non-enthusiast platforms. On the other hand, DDR4 speeds at release competed with DDR3 speeds at end of life, so if the CPU's can support it, we might be able to scale our memory up to 4 GHz or 5 GHz before long.

[QUOTE=Prime95;389532]My understanding is DDR4 does not imply quad channel[/QUOTE]

Hmm, that's probably true... but it probably will be still better than DDR3.

[QUOTE=TheMawn;389534]
Is that for the FFT?
[/QUOTE]
Yes.
[QUOTE=TheMawn;389534]
Can two workers share the same data if their FFT size is the same?
[/QUOTE]
No. That's like asking if two cars can use the same engine because they're the same kind of car. :smile:

[QUOTE=Dubslow;389543]No. That's like asking if two cars can use the same engine because they're the same kind of car. :smile:[/QUOTE]

Very well, thanks.

[QUOTE=TheMawn;389534]I think you've said before that there's a bunch of sine and cosine data that takes up a bunch of space. Is that for the FFT? Can two workers share the same data if their FFT size is the same?[/QUOTE]

The sin/cos data could be shared among two or more FFTs of the same size. The weighting factors cannot be shared.

Unfortunately, the bulk of the memory bandwidth (IIRC 95+%) is used reading and writing the FFT data. I once implemented sharing the sin/cos data and the speed difference was not measurable.

[QUOTE=Prime95;389570]I once implemented sharing the sin/cos data and the speed difference was not measurable.[/QUOTE]

Ah. That's unfortunate.