Bitcoin miner for GIMPS...
 

Just got the following ad from Memory Ten.

Assuming that the GIMPS software existed for it, how much might this baby produce (LL, TF) on a per-day basis? :smile:




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[COLOR=#606060][COLOR=black]Now check out the price:[/COLOR]

[SPOILER]$3,200.00[/SPOILER] :shock:

[/COLOR]
[COLOR=black]Next question: would something like this be worth writing specialized software for?[/COLOR]

Rodrigo

If it would work at all.

ASIC's are designed and made ONLY for mining whatever, they are useless(can't) for anything else.

That's too bad. :sad:

Does the inability have to do with the hardware itself? (Meaning, there would be no way to, umm, repurpose the machine.)

Rodrigo

Perhaps you would benefit from googling the acronym "ASIC"- Application Specific Integrated Circuit. Kracker meant what he said with the ONLY.

Perhaps you mean to ask "how fast could we build an ASIC for Prime95?" That is a fair question, though cost prohibits it as anything beyond a what-if.

[QUOTE=Rodrigo;374663]That's too bad. :sad:

Does the inability have to do with the hardware itself? (Meaning, there would be no way to, umm, repurpose the machine.)

Rodrigo[/QUOTE]
Exactly. It is hardware which is special designed to do SHA256 hashing. Like a hard-wired GPU. Thousands of small registers which can add and shift, and nothing else, and there is no way to make them doing something else without using hammer and pliers. Of course, this need an OS interface to put something in and extract the results, but that's all. Inside of the box, it can only do SHA hashing. When bitcoin is gone (if ever), you can use the machine as a rusty ornament for your garden. There may be possible to make an asic for TF (in fact is quite easy! no big memory requirement, hardware sieving (shift and set bit) etc. But convincing any asic in any way to make DP calculus (LL testing) is a HARD job even for the most advanced design houses in the world (I mean the guys who build asics for a living, like xilinx, altera, etc)

Thanks for the scoop, VBCurtis and LaurV.

Would it be fair to say that, because of the way this machine is designed, there isn't even any way to guesstimate how many GHz-days/day it would throughput -- if it could? (Sort of like asking, say, at how many MPH a thermostat could propel a hockey puck.) And (therefore) that such a question would be meaningless? These are the suggestions I take from the responses.

Rodrigo

I think the best comparison we can do is to look at Bitcoin mining speeds on GPUs and compare that to TF speeds on GPUs. The Radeon HD 7970 has benchmarks for both [URL="https://en.bitcoin.it/wiki/Mining_hardware_comparison#Graphics_cards"]Bitcoin[/URL] and [URL="http://www.mersenne.ca/mfaktc.php?show=466&sort=ghdpd"]TF[/URL], so I'll use that. It gets about 700 MHash/sec and about 400 GHz-days/day. So if we were to assume (probably wrong) that an ASIC for TF (as others have said, this would have to be different hardware from a SHA256 ASIC) could have the same difference, that ASIC would be (1300 GH/0.7 GH=) 1,857 times faster, or 742.8 THz-days/day. The whole of GIMPS currently is at ~77 THz-days/day (GPUto72 is around 15 THz of that). If we had [I]one[/I] of those monsters going for us (guessing it's 50 times faster than our current TF abilities), we could probably TF to about 79 bits instead of 73/74, which would find around 7.5% more factors.

There are all sorts of reasons why this is probably wrong...I said [I]best[/I] comparison, not [I]good[/I] comparison. To actually know, we'd probably need some experts in ASIC design and TF algorithms to design and/or actually create some ASICs for us.

And you'd need a whole other ASIC for LL, where you'd probably not get nearly as much of a speed improvement. But, since it could be applied to the longer test, instead of the diminishing returns you get in TF, it could be more useful to GIMPS.

[QUOTE=Rodrigo;374669]Thanks for the scoop, VBCurtis and LaurV.

Would it be fair to say that, because of the way this machine is designed, there isn't even any way to guesstimate how many GHz-days/day it would throughput -- if it could? (Sort of like asking, say, at how many MPH a thermostat could propel a hockey puck.) And (therefore) that such a question would be meaningless? These are the suggestions I take from the responses.

Rodrigo[/QUOTE]

Yeah, I think you're right. But that doesn't mean we can't wildly speculate anyway!

Any comparison is useless. These things are not even remotely comparable. Don't even try. A SHA ASIC simply cannot ever be repurposed to do anything except SHA. Don't confuse this with an FPGA or a CPU or a GPU. It is none of these things and can't be made to emulate one either.

Actually the thing that caught my attention was the 2-horse-power rating with only air cooling at 55dB. How is that possible?

That chart covers it pretty well, thanks! Amazing what sorts of things people put together for the 'Net.

[QUOTE=Mini-Geek;374682]But that doesn't mean we can't wildly speculate anyway![/QUOTE]

That's what makes it fun! :grin:

Rodrigo

[QUOTE=retina;374692]Any comparison is useless. These things are not even remotely comparable. Don't even try. A SHA ASIC simply cannot ever be repurposed to do anything except SHA. Don't confuse this with an FPGA or a CPU or a GPU. It is none of these things and can't be made to emulate one either.

Actually the thing that caught my attention was the 2-horse-power rating with only air cooling at 55dB. How is that possible?[/QUOTE]

One does wonder. Always in order to heed the warning at the very top of the chart on the page that Mini-Geek linked to:

[QUOTE]
[B][B]Note that products which have not shipped, especially by new vendors, may be scams! Be sure to research any of these intensely before giving them any money.[/B] [/B]
[/QUOTE]

Maybe this vendor has been in operation for a while, but anyway it's not something I'd jump into without asking around first.

Another item that suggests "proceed with caution" is the disclaimer on the [URL="http://www.visionman.com/product_info_2.php?products_id=9310"]product page[/URL]:


[QUOTE] [LIST][*]Due to the highly-specialized nature of these machines, they are [B]non-cancellable[/B] and [B]non-returnable[/B].[/LIST][/QUOTE]

Rodrigo

It would certainly be cool if there was an ASIC for trial factoring or Lucas-Lehmer tests. Unfortunately, I don't think we'll see any custom GIMPS hardware anytime soon because there is no monetary incentive for developing it. People don't earn money crunching for GIMPS as they would mining Bitcoins.

[QUOTE=ixfd64;374713]It would certainly be cool if there was an ASIC for trial factoring or Lucas-Lehmer tests. Unfortunately, I don't think we'll see any custom GIMPS hardware anytime soon because there is no monetary incentive for developing it. People don't earn money crunching for GIMPS as they would mining Bitcoins.[/QUOTE]I'm trying to teach myself Verilog and FPGA design. Perhaps a TF implmentation may be forthcoming. Don't bet on it happening any time soon, unless anyone else wants to work with me.

Even so, it's unlikely (IMAO) that a sufficiently fast implementation will happen any time soon.

[QUOTE=ixfd64;374713]People don't earn money crunching for GIMPS as they would mining Bitcoins.[/QUOTE]

Good thing, too, because the only thing worse than spending lots of time writing custom code for a specialized problem and not getting paid for it, is doing so for a tech-geek fad which serves no remotely useful purpose except perhaps to enrich one's local electric utility.

(And before the bitCon fanbois pipe up with their delusions of "decentralized money beyond government reach, dude", see [url=http://www.zerohedge.com/node/488930]here[/url] for recent analysis of the fraud/scam aspects of BTC, and [url=http://jessescrossroadscafe.blogspot.com/2014/05/gold-daily-and-silver-weekly-charts-why.html]here[/url] for why governments would love nothing better than an all-digital currency paradigm - under their control, of course, which is the inevitable price for any such currency to become truly wide-scale adopted.)

[QUOTE=ewmayer;374726]Good thing, too, because the only thing worse than spending lots of time writing custom code for a specialized problem and not getting paid for it, is doing so for a tech-geek fad which serves no remotely useful purpose except perhaps to enrich one's local electric utility.[/QUOTE]

Oh, I'm not sure you are correct...

Being able to experiment with distributed systems, software, hardware and social media might have some up-side...

I believe a book was recently written about exactly this....

GPUs are optimized for single precision arithmetic. So it is possible to have a big boost if using ASIC for doing large multiplies.

When using hardware, there is no need to use FFT. You can use the hardware to perform multiplication of extremely big numbers by using, say, 1024-bit hardware multipliers and then multiply and add 1024-bit chunks.

For numbers about M102400000, the multiplication could be done in k*100000 clock cycles, where k is a very small number. Of course you would need 100000 of these multipliers operating in parallel.

To fix the idea suppose k=5, frequency = 1GHz (which it is not too fast).

Then the complete LL would require 5*100000*102400000/10[SUP]9[/SUP] = 51200 seconds.

This would need about 1 billion gates to work. I think it is too much for current technology, especially if we want to use this method up to M999999999, but the speedup would be awesome.

[QUOTE=alpertron;374738]When using hardware, there is no need to use FFT. You can use the hardware to perform multiplication of extremely big numbers by using, say, 1024-bit hardware multipliers and then multiply and add 1024-bit chunks.[/QUOTE]I think you would be better off using NTT. Even using Karatsuba here would be rather silly for numbers of that size.

Building an ASIC means you are paying someone to build a custom chip for you; in fact you are paying someone to retool an entire production line in an overseas factory to build a custom chip for you. Depending on how badass your chip is, the one-time cost (NRE, or non-recurring-engineering) for doing that can be millions of dollars. The software that even lets you design a large ASIC can itself cost millions of dollars.

By comparison, building your logic into an FPGA costs a few hundred dollars for a development board, software that is usually downloaded for free, and a ton of your time. The downside is that FPGAs are much more constrained compared to ASICs, both in the amount of logic they have and the speed at which that logic runs. A nice latter-day Xilinx FPGA has hundreds of 17-bit multipliers and several megabytes of on-chip memory, running at ~600MHz, but those chips cost $3k-10k each. That kind of money can buy you a room full of PCs with GPUs.

[QUOTE=ewmayer;374726]And before the bitCon fanbois pipe up with their delusions of "decentralized money beyond government reach, dude",[/QUOTE]
I don't wanna stole the thread, what you show there is what EVERY Forex broker does. Should that mean the actual currencies we use (EUR, USD, JPY, etc) are all scams? I remember the FXCM scandal in 2003 or so (yes, I was trading for so long, didn't get rich, because I didn't risk a lot, but didn't get swapped away too, at the time it was called FX LTC or something like that, they were my first broker, to which I lost $3800 in few months, in few different accounts, it was how I started). That scandal sounded the same as the one you linked (about mtgox) except the numbers.

Now, after the thing gone (I didn't have any money with mtgox, sorry for the people who lost their money there - that's life!, I still have my bitcoins, didn't sell them) I see this as a positive thing for the coin itself. Guys trying to profit from it were swapped away. So what?

In fact, this confirm what I said before. They were trying to grab the control of the bitcoin market for themselves, they got their asses shaved. The rest is collateral damage. Bitcoin is still well, thanks for asking...

Indeed, in the sense that their "value" derives from a set of assumptions and promises, "faith" if you will, all fiat currencies are scams. But in this arena there is a crucial difference between government-mandated scams and 3rd-party scams. I know it's not fair, just as death and taxes aren't fair.

Re. the sellers of custom [strike]digit-twiddling[/strike]mining hardware, a question: If it is so easy to make profits from mining on said equipment, why would said companies ever want to part with it? Why not keep it and make huge profits by their own large-scale mining? Their profit potential would even be quite a bit higher than that of Joe Schmoe retail-customer Miner, due to the fact that they get the gear at cost, and can take advantage of similar economies of scale in mining as exist in the manufacture of said equipment.

[QUOTE=ewmayer;374801]Re. the sellers of custom [strike]digit-twiddling[/strike]mining hardware, a question: If it is so easy to make profits from mining on said equipment, why would said companies ever want to part with it? Why not keep it and make huge profits by their own large-scale mining? Their profit potential would even be quite a bit higher than that of Joe Schmoe retail-customer Miner, due to the fact that they get the gear at cost, and can take advantage of similar economies of scale in mining as exist in the manufacture of said equipment.[/QUOTE]It has been asked before.

[url]http://www.mersenneforum.org/showthread.php?p=368499#post368499[/url]

[QUOTE=retina;374815]It has been asked before.

[url]http://www.mersenneforum.org/showthread.php?p=368499#post368499[/url][/QUOTE]

But it's not yet been answered by any of our latter-day 49ers.

[QUOTE=ewmayer;374801]Re. the sellers of custom [strike]digit-twiddling[/strike]mining hardware, a question: If it is so easy to make profits from mining on said equipment, why would said companies ever want to part with it? Why not keep it and make huge profits by their own large-scale mining? Their profit potential would even be quite a bit higher than that of Joe Schmoe retail-customer Miner, due to the fact that they get the gear at cost, and can take advantage of similar economies of scale in mining as exist in the manufacture of said equipment.[/QUOTE]

Because they can shift the risk to their customers. They might both come out ahead. They might not. "We can create hardware for $X and sell it for $Y" is a much better proposition than "We can create hardware for $X and hopefully in the future sell the bitcoins it produces for $Z". (X < Y < Z) And, for the appropriately risk-tolerant customers (a.k.a. gamblers), "I can buy hardware for $Y and hopefully sell the bitcoins for $Z" is acceptable.

Plus, if the company was able to build enough hardware to make it over 50% of the mining power, the community would be suspicious of possible 51% attacks...you don't want to shoot yourself in the foot by tanking bitcoin's price after spending millions on custom hardware. (letting the hardware be distributed removes/lowers this risk)

[QUOTE=ewmayer;374819]But it's not yet been answered by any of our latter-day 49ers.[/QUOTE]They obviously only sell units that have been fully "burned-in" at the factory for a year or two. And when the new hotness units are ready to take over from the old POS units they sell the POS units and start burning in the new hotnesses. So these "new" 28nm units have been "tested" for a while, and the not-yet-for-sale 20nm units are currently being factory "tested". If you blow out the dust, put in new fans with a shiny casing then no one would be able to tell how long it has been "burning-in".

All those may be good reasons. Like "why people are selling/buying MT5 trading experts?", if those are so good to make profit, why the sellers don't use them by themselves to make lots of money? Imagine I could make an expert to double my account every year, should I be so moron to sell it? No, I would keep it secret and guard it with my own life. And after making lots of money I will retire on a nice beach... The reality is that the mother of stupid and credulous people is always pregnant, and the "experts market" is still very profitable (I used to do MT5 tools and sell them too, and even if I am very honest in telling to the people what the expert can do and what it can not do, they are still wanting to buy it, and they dream to get rich overnight).

Back to bitcoin, [URL="https://bitcoinwisdom.com/bitcoin/difficulty"]this[/URL] may be the real reason why people sell the hardware. Stay with your mouse on the thumbnail called "9 months". Every piece of miner you put in the net will increase the difficulty. You buy the hardware now and expect to recover your money in a month or two, but other people think the same, and the difficulty is skyrocketing, so you will need one or two years to come to any profit. Anything can happen in this time, and the risk is big. This may happen to the hardware producer too. And then he does what he knows best: produce hardware and sell it. With no risk, and big profit, you don't imagine that the three blades inside that box cost 3000 dollars to be produced. They are most likely to cost 100 dollars (production cost only) or so. Plus a power supply and few fans in a box. As someone said above, not everybody has the same risk affinity. If you are lucky, you can find a block in first month (about $16K at the actual prices) and you will get the money back with 400% return. If not, you still can crunch for years, or join a pool and do few dollars each day. With 1.3TH you can do about $5 per day (deducting electricity at $0.25, and 1.5KW consumption, includes the computer too, to maintain a wallet, etc, or the net hub, etc). So, you may need more than a year to "recover" the ~$3500 spent on hardware.

It is [B]*not*[/B] a recipe to get rich fast. It is a big risk. But people don't understand this.

Hi All,

I agree with LaurV. Bitcoin is risky business and not a sound investment.

Regards,
Matt

I concur. Bitcoin is for those who are willing to take a risk for the sake of blazing a new trail and don't mind losing their shirts in the process, if it comes to that.

As a straight investment, it was probably OK if you got in at the start (but then, who knew about it at the time?).

My main interest in bringing up the topic was to examine the possibility of using one of those Bitcoin miners for GIMPS, but that's been well answered. (Too bad!)

Now, if somehow we could get GHz-days to be accepted as a digital currency, things might turn out differently. :cool: What would we call it -- Gigahertzcoin? Primecoin?? Mersennecoin??? Bitcoin? -- oh wait, that's already taken...

Rodrigo

Coming back to the original discussion in the thread, Altera just published (today! I am subscribed to their news feed) a [URL="http://www.altera.com/literature/wp/wp-01222-understanding-peak-floating-point-performance-claims.pdf"]very interesting paper[/URL] (entry level, general knowledge, anybody can read it, you don't need math or programming knowledge to understand it) about floating point computing in FPGAs, where a GPU is compared against a DSP and a FPGA. For example, you can read there (the "conclusion" on page 9) about their newest toys which can reach 10 [B][U]tera[/U][/B] flops of... MP (?) calculus (let's call it MP, this term I just invented now, "mid-precision", I didn't know what to write, SP or DP, because they use an intermediary size, with maximum 36 bits of mantissa, so it is nor SP, neither DP) performance. This is something like 10 good GPUs together (or say, 3 Titan Black together, or 3 Tesla K20 together), for just a fraction of power. Yet, the price of such toys are prohibitive.

Following the link through the document reveals more, for who is interested. For example the link about building radar systems on the last page shows you some insight into the FFT calculus in a FPGA and GPU, applied to, of course, radar systems.

Even though there is less financial incentive to develop custom hardware for GIMPS, I think it's still a good idea to talk to ASIC designers. A lot of companies support non-profit groups and may be willing to undertake such a project for a lower fee, if not for free.

[url]http://arstechnica.com/security/2014/06/bitcoin-security-guarantee-shattered-by-anonymous-miner-with-51-network-power/[/url]

[url=https://medium.com/@octskyward/the-resolution-of-the-bitcoin-experiment-dabb30201f7#.et2qupbdj]The resolution of the Bitcoin experiment[/url] | Medium

A.k.a. "how perfectly conceived systems fail in the real world".

I actually purchased a decent FPGA board just for the purposes of "playing with" a TF algorithm and comparing it to the GPUs.

Doing custom LL on an ASIC would be a very cool project - however as others have mentioned beyond incredibly expensive....

There may be more broad market value to an ASIC that could do VERY fast FFTs, which we could use....

[QUOTE=airsquirrels;422753]I actually purchased a decent FPGA board just for the purposes of "playing with" a TF algorithm and comparing it to the GPUs[/QUOTE]

What were the results like?

[QUOTE=airsquirrels;422753]I actually purchased a decent FPGA board just for the purposes of "playing with" a TF algorithm and comparing it to the GPUs.

Doing custom LL on an ASIC would be a very cool project - however as others have mentioned beyond incredibly expensive....

There may be more broad market value to an ASIC that could do VERY fast FFTs, which we could use....[/QUOTE]

Also, something which may be interesting...
[url]http://www.pcworld.com/article/3006601/components-processors/intels-first-server-chip-with-performance-boosting-fpga-to-ship-early-next-year.html[/url]

Intel looks like they'll be releasing hybrid Xeon/FPGA chips this year (Q1 apparently).

to be honest cost is the main issue based on what's in the thread already however I do think it is possible to some extent because of Laurv's posting about shifts and adds technically with a bittest those could be turned into a way to do TF and LL at very least just not efficiently. squaring can be done using bit shifts and subtraction is just like adding a negative number to something. it's really the bit testing needed that would make it fail I think that and it's inefficiency. because although it works without bit testing to square mersenne numbers not so much outside of them:

[CODE](08:58) gp > 5<<2+5<<0
%1 = 25
(08:59) gp > 7<<2+7<<1+7<<0
%2 = 49[/CODE]

they both can be squared using bit shifts the problem is testing to which amounts they need to be shifted by otherwise it becomes 5*7 if you shift 5 by all 3 of [0,1,2]. And technically subtraction without a counter is like saying these numbers are congruent mod a number. but these methods take too long to perform efficiently.

[QUOTE=airsquirrels;422753]There may be more broad market value to an ASIC that could do VERY fast FFTs, which we could use....[/QUOTE]

Yes. They're called DSPs.

[QUOTE=xilman;374722]I'm trying to teach myself Verilog and FPGA design. Perhaps a TF implmentation may be forthcoming. Don't bet on it happening any time soon, unless anyone else wants to work with me.

Even so, it's unlikely (IMAO) that a sufficiently fast implementation will happen any time soon.[/QUOTE]

I did FPGA design back in college... pretty basic stuff and the end goal of the class was the design of a simple 4-bit limited-op CPU. Xilinx chips and I forget the name of the software we used.

It was pretty interesting to work out the design and then hook up a programmer and, for testing, using a push-button clock (so we could step through cycle-by-cycle and check inputs/outputs).

It did open my eyes to the possibilities of such things for custom applications, and I'm pretty sure the custom ASICs for bitcoin mining are along those lines. It made me wonder if the ASICs used in them aren't really FPGAs that could be reprogrammed with a different function. Or do they really such a huge market that they custom fabricate crap like that?

[QUOTE=Madpoo;422826]I did FPGA design back in college... pretty basic stuff and the end goal of the class was the design of a simple 4-bit limited-op CPU. Xilinx chips and I forget the name of the software we used.

It was pretty interesting to work out the design and then hook up a programmer and, for testing, using a push-button clock (so we could step through cycle-by-cycle and check inputs/outputs).

It did open my eyes to the possibilities of such things for custom applications, and I'm pretty sure the custom ASICs for bitcoin mining are along those lines. It made me wonder if the ASICs used in them aren't really FPGAs that could be reprogrammed with a different function. Or do they really such a huge market that they custom fabricate crap like that?[/QUOTE]

There used to be a market for FPGA-based mining hardware, but the ASICs left them in the dust.

[QUOTE=axn;422786]Yes. They're called DSPs.[/QUOTE]

Except most DSP chips for commercial applications have what I think you might call "interesting" precision. I read an article the other day about a new DSP with some kind of FFT algorithm that could do compression/decompression really fast and efficient, but it depends entirely on the fact that audio and video has a lot of empty frequencies. My takeaway was that it would suck at doing anything with more random data like what happens during LL.

(my apologies for probably mangling the underlying concept...I skimmed the article)

[QUOTE=science_man_88;422785]subtraction is just like adding a negative number to something.[/QUOTE]

Holy crap! I'm gonna need to rewrite half my code to take advantage of that.

Re. the rest of your clever scheme: so to multiply a pair of GIMPS-wavefront-sized inputs, we simply need to do 70-million-or-so 70-million-bit-wide shift-and-adds ... got any similarly genius ideas for the ensuing modular reduction step? And that doesn't even take advantage of the fact that for LL testing we are *squaring* the input, rather than general-multiplying ... I bet we could get a further speedup by taking advantage of that. See, this is the reason I spend time around here...

[QUOTE=ewmayer;422834]Holy crap! I'm gonna need to rewrite half my code to take advantage of that.

Re. the rest of your clever scheme: so to multiply a pair of GIMPS-wavefront-sized inputs, we simply need to do 70-million-or-so 70-million-bit-wide shift-and-adds ... got any similarly genius ideas for the ensuing modular reduction step? And that doesn't even take advantage of the fact that for LL testing we are *squaring* the input, rather than general-multiplying ... I bet we could get a further speedup by taking advantage of that. See, this is the reason I spend time around here...[/QUOTE]
I also said:
"just not efficiently." modular reduction could be as simple as the subtraction step done in the thread I made in the lounge [url]http://mersenneforum.org/showthread.php?t=20803[/url] as all a modular result tells you is what he remainder on division is and you can get there using subtraction. oh and the shifts can potentially be decreased as they are being made using subtraction of the exponent because the powers of two that are a multiple of the next power of two will all be 1 for remainder. anyways enough with this self defeating post.

[QUOTE=science_man_88;422836]...anyways enough with this self defeating post.[/QUOTE]

Ever hear of the saying to the effect of "when you find yourself in a hole..."? [Hint: put down the shovel.]

[QUOTE=ewmayer;422848]Ever hear of the saying to the effect of "when you find yourself in a hole..."? [Hint: put down the shovel.][/QUOTE]

I was pointing out that technically it's not the lack of instructions that would be the downfall it would be the way it's wired and the order it's forced into.

Still digging, I see.

[Hint-which-will-surely-be-ignored: Fundamentally quadratic complexity versus subquadratic.]

[QUOTE=ewmayer;422850]Still digging, I see.

[Hint-which-will-surely-be-ignored: Fundamentally quadratic complexity versus subquadratic.][/QUOTE]

you can make a test version that uses 2*x^2-1 which is nearly the 2*x^2 used in the TF when the bit is 1. and as I've said through PM I've made code that can do both before I'm just not sure where I posted it. Also like I've said through PM I've also tried to use what the basic idea shows us to try and make a test within the mersennes themselves. I have also tried to do this on the forum and I can't remember where it is. found the code :[url]http://mersenneforum.org/showpost.php?p=403399&postcount=396[/url]

[QUOTE=ewmayer;422848][Hint: put down the shovel.][/QUOTE]
[URL="http://www.urbandictionary.com/define.php?term=Woosh"]Woosh[/URL]!...
[QUOTE=ewmayer;422850][Hint-which-will-surely-be-ignored: Fundamentally quadratic complexity versus subquadratic.][/QUOTE]
Woosh!...

[QUOTE=Batalov;422854]Woosh!...[/QUOTE]

Please forgive him. He's Canadian.

I suppose a national anthem whose wording opens with "Oh, Canada! We stand on cars and freeze..." is rather a big tip-off, innit?

[QUOTE=chalsall;422857]Please forgive him. He's Canadian.[/QUOTE]
I don't think that's right. I am pretty sure that he is ex-Austrian-American.

[QUOTE=ewmayer;422860]I suppose a national anthem whose wording opens with "Oh, Canada! We stand on cars and freeze..." is rather a big tip-off, innit?[/QUOTE]

Right, eh?

[QUOTE=ewmayer;422860]I suppose a national anthem whose wording opens with "Oh, Canada! We stand on cars and freeze..." is rather a big tip-off, innit?[/QUOTE]

you are already on the 7th line by the time something even remotely close sounding comes up. I was going to go over potential structure we could use but what ever.

[QUOTE=ewmayer;422834]so to multiply a pair of GIMPS-wavefront-sized inputs, we simply need to do 70-million-or-so 70-million-bit-wide shift-and-adds ... [/QUOTE]

So we expand this VHDL to 70 million? We are gonna need a supercomputer for ModelSim.

[CODE]
-- Project Step 8 - Integrating Register and ALU in a datapath
--
-- NAME:Rob Pancoast
--
-------------------------------------------------------------------------------
-- BE SURE TO TURN IN ALL CODE USED!!!
-------------------------------------------------------------------------------
-- Enter ENTITY/ARCHITECTURE for datapath here.
-- (you can use the package that you used in step 6 which
-- should still be in the library)
-------------------------------------------------------------------------------

package step8_package is

TYPE operations IS (op_A,op_B,op_notA,op_notB,op_AxorB,op_AorB,op_AandB,
op_AnandB,op_AxnorB,op_0,op_1,op_incA,op_incB,op_decA,
op_decB,op_negA,op_negB,op_AplusB,op_AplusBwC,
op_AminB,op_AminBwC,op_BminA);
end step8_package;

package body step8_package is
end step8_package;

LIBRARY IEEE;
USE work.step8_package.all;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY alu_16std_logic IS
PORT ( alu_op : IN operations;
a,b : IN std_logic_vector(15 downto 0);
Cin : IN std_logic;
Zout : INOUT std_logic_vector(15 downto 0);
Cout,n,Z : OUT std_logic);
END alu_16std_logic;

ARCHITECTURE ALU16std_logicpwn OF alu_16std_logic IS
PROCEDURE binadd (l,r : IN std_logic_vector;
cin : IN std_logic;
sum : OUT std_logic_vector;
cout : OUT std_logic);
PROCEDURE binadd (l,r : IN std_logic_vector;
cin : IN std_logic;
sum : OUT std_logic_vector;
cout : OUT std_logic) IS
VARIABLE carry : std_logic; --internal variable carry
BEGIN
carry := cin;
FOR i IN l'reverse_range LOOP
IF (l(i)='0' and r(i)='0' and carry='0') THEN -- case for 0
sum(i):='0';
carry:='0';
ELSIF ((l(i)='1' and r(i)='0' and carry='0') or (l(i)='0' and r(i)='1' and carry='0') or (l(i)='0' and r(i)='0' and carry='1')) THEN -- case for 1
sum(i):='1';
carry:='0';
ELSIF ((l(i)='1' and r(i)='1' and carry = '0') or (l(i)='1' and r(i)='0' and carry='1') or (l(i)='0' and r(i)='1' and carry='1')) THEN -- case for 2
sum(i):='0';
carry:='1';
ELSE --case for 3
sum(i):='1';
carry:='1';
END IF;
END LOOP;
cout := carry;
end binadd;

PROCEDURE neg (num : IN std_logic_vector;
negnum : OUT std_logic_vector;
pcout : OUT std_logic);
PROCEDURE neg (num : IN std_logic_vector;
negnum : OUT std_logic_vector;
pcout : OUT std_logic) IS
BEGIN
-- invert num, add it to 0 with Cin =1
binadd(not(num),(not num and num),'1',negnum,pcout);
end neg;


PROCEDURE binsub (numero,subtractness : IN std_logic_vector;
brwin : IN std_logic;
sum : OUT std_logic_vector;
brwout : OUT std_logic);
PROCEDURE binsub (numero,subtractness : IN std_logic_vector;
brwin : IN std_logic;
sum : OUT std_logic_vector;
brwout : OUT std_logic) IS
VARIABLE brw : std_logic; --internal variable carry
VARIABLE concat : std_logic_vector (2 downto 0);
BEGIN
brw := brwin;
FOR i IN numero'reverse_range LOOP
concat:= numero(i) & subtractness(i) & brw;
CASE concat IS
WHEN "000" => sum(i):= '0'; brw:= '0'; --0-(0 + 0)
WHEN "001" => sum(i):= '1'; brw:= '1'; --0-(0+1)
WHEN "010" => sum(i):= '1'; brw:= '1'; --0-(1+0)
WHEN "011" => sum(i):= '0'; brw:= '1'; --0-(1+1)
WHEN "100" => sum(i):= '1'; brw:= '0'; --1-(0+0)
WHEN "101" => sum(i):= '0'; brw:= '0'; --1-(0+1)
WHEN "110" => sum(i):= '0'; brw:= '0'; --1-(1+0)
WHEN "111" => sum(i):= '1'; brw:= '1'; --1-(1+1)
WHEN OTHERS => NULL;
END CASE;
END LOOP;
brwout := brw;
end binsub;
BEGIN

PROCESS (A, B, Cin, alu_op)
Variable Resulttmp : std_logic_vector (15 downto 0);
variable CoutTmp : std_logic;
BEGIN
CASE alu_op IS
WHEN op_A => Zout<= A; Cout <= '0'; --op_A
WHEN op_B => Zout<= B; Cout <= '0'; --op_B
WHEN op_notA => Zout<= not A; Cout <= '0'; --op_notA
WHEN op_notB => Zout<= not B; Cout <= '0'; --op_notB
WHEN op_AxorB => Zout<= A xor B; Cout <= '0'; --op_AxorB
WHEN op_AorB => Zout<= A or B; Cout <= '0'; --op_AorB
WHEN op_AandB => Zout<= A and B; Cout <= '0'; --op_AandB
WHEN op_AnandB => Zout<= A nand B; Cout <= '0'; --op_AnandB
WHEN op_AxnorB => Zout<= A xnor B; Cout <= '0'; --op_AxnorB
WHEN op_0 => Zout<= "0000000000000000"; Cout <= '0'; --op_0
WHEN op_1 => Zout<= "1111111111111111"; Cout <= '0'; --op_1
WHEN op_incA => binadd(A,"0000000000000000",'1',resulttmp, CoutTmp); Zout <= resulttmp; Cout <= CoutTmp; --op_incA
WHEN op_incB => binadd(B,"0000000000000000",'1',resulttmp, CoutTmp); Zout <= resulttmp; Cout <= CoutTmp; --op_incB
WHEN op_decA => binsub(A,"0000000000000000",'1',resulttmp, CoutTmp); Zout <= resulttmp; Cout <= CoutTmp; --op_decA
WHEN op_decB => binsub(B,"0000000000000000",'1',resulttmp, CoutTmp); Zout <= resulttmp; Cout <= CoutTmp; --op_decB
WHEN op_negA => neg(A, resulttmp, CoutTmp); Zout <= resulttmp; Cout <= CoutTmp; --op_negA
WHEN op_negB => neg(B, resulttmp, CoutTmp); Zout <= resulttmp; Cout <= CoutTmp; --op_negB
WHEN op_AplusB => binadd(A,B,Cin,resulttmp, CoutTmp); Zout <= resulttmp; Cout <= CoutTmp; --op_AplusB
WHEN op_AplusBwC => binadd(A,B,Cin,resulttmp, CoutTmp); Zout <= resulttmp; Cout <= CoutTmp; --op_AplusBwC
WHEN op_AminB => binsub(A,B,Cin,resulttmp, CoutTmp); Zout <= resulttmp; Cout <= CoutTmp; --op_AminB
WHEN op_BminA => binsub(B,A,Cin,resulttmp, CoutTmp); Zout <= resulttmp; Cout <= CoutTmp; --op_BminA
WHEN OTHERS => NULL;
END CASE;
--if Zout(15)/='1' or Zout(15)/='0' then n <= '0';
--else N <= Zout(15);
--end if;
N <= Zout(15);
if zout = "0000000000000000" then z <= '1';
else z <= '0';
end if;
END PROCESS;
END ALU16std_logicpwn;

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE work.step8_package.all;
ENTITY DataPAthCoastn IS
PORT (ABUS,BBUS : INOUT std_logic_vector (15 downto 0) := "ZZZZZZZZZZZZZZZZ";
Aregload,Bregload,Aregdrive,Bregdrive,Cin : IN std_logic;
A_ALUload,B_ALUload,A_ALUdrive,B_ALUdrive : IN std_logic;
C,N,Z : OUT std_logic;
alu_op : IN operations;
AregNo,BregNo : IN integer := 0);
END DataPAthCoastn;
-------------------------------------------------------------------------------
-- Enter your Architecture for a the datapath here
-------------------------------------------------------------------------------
ARCHITECTURE datpatharch OF DataPAthCoastn IS
TYPE regs_type IS array (0 to 15) of std_logic_vector (15 downto 0);
signal a,b,zout : std_logic_vector(15 downto 0) := "ZZZZZZZZZZZZZZZZ";
COMPONENT alu_16std_logic
PORT ( alu_op : IN operations;
a,b : IN std_logic_vector(15 downto 0);
Cin : IN std_logic;
Zout : INOUT std_logic_vector(15 downto 0);
Cout,n,z : OUT std_logic);
END COMPONENT;
FOR ALL : alu_16std_logic USE ENTITY WORK.alu_16std_logic(ALU16std_logicpwn);
BEGIN
alu16good : alu_16std_logic PORT MAP(alu_op,A,B,Cin,Zout,C,n,z);
PROCESS (ABUS,BBUS,Aregload,Bregload,Aregdrive,Bregdrive,AregNo,BregNo,A_ALUload,B_ALUload,A_ALUdrive,B_ALUdrive)
VARIABLE RegSet : regs_type := ("ZZZZZZZZZZZZZZZZ","ZZZZZZZZZZZZZZZZ", -- set initial state to highz
"ZZZZZZZZZZZZZZZZ","ZZZZZZZZZZZZZZZZ","ZZZZZZZZZZZZZZZZ","ZZZZZZZZZZZZZZZZ",
"ZZZZZZZZZZZZZZZZ","ZZZZZZZZZZZZZZZZ","ZZZZZZZZZZZZZZZZ","ZZZZZZZZZZZZZZZZ",
"ZZZZZZZZZZZZZZZZ","ZZZZZZZZZZZZZZZZ","ZZZZZZZZZZZZZZZZ","ZZZZZZZZZZZZZZZZ",
"ZZZZZZZZZZZZZZZZ","ZZZZZZZZZZZZZZZZ");

BEGIN
IF (Aregload='1' AND Aregload'event) THEN -- load A on rising edge of Aregload
RegSet(AregNo):=ABUS;
END IF;
IF (A_ALUload='1' AND A_ALUload'event) THEN -- load A on rising edge of A_ALUload
if a="ZZZZZZZZZZZZZZZZ" then a <= "0000000000000000";
else a<=ABUS;
END IF;
END IF;
IF (Bregload='1' AND Bregload'event) THEN -- load B on rising edge of Bregload
RegSet(BregNo):=BBUS;
END IF;
IF (B_ALUload='1' AND B_ALUload'event) THEN -- load B on rising edge of B_ALUload
if b="ZZZZZZZZZZZZZZZZ" then b <= "0000000000000000";
else b<=BBUS;
END IF;
END IF;
IF (Aregdrive='0') THEN -- drive reg(n) value to A bus when Aregdrive = low
ABUS<=RegSet(AregNo);
END IF;
IF (A_ALUdrive='0') THEN -- drive reg(n) value to A bus when A_ALUdrive = low
ABUS<=Zout;
END IF;
IF (Bregdrive='0') THEN -- drive reg(n) value to B bus when Bregdrive = low
BBUS<=RegSet(BregNo);
END IF;
IF (B_ALUdrive='0') THEN -- drive reg(n) value to B bus when B_ALUdrive = low
BBUS<=Zout;
END IF;
IF (Aregdrive='1' AND Aregdrive'event) THEN -- load hiz to A bus on rising edge of Aregdrive
ABUS<="ZZZZZZZZZZZZZZZZ";
END IF;
IF (A_ALUdrive='1' AND A_ALUdrive'event) THEN -- load hiz to A bus on rising edge of A_ALUdrive
ABUS<="ZZZZZZZZZZZZZZZZ";
END IF;
IF (Bregdrive='1' AND Bregdrive'event) THEN -- load hiz to B bus on rising edge of Bregdrive
BBUS<="ZZZZZZZZZZZZZZZZ";
END IF;
IF (B_ALUdrive='1' AND B_ALUdrive'event) THEN -- load hiz to B bus on rising edge of B_ALUdrive
BBUS<="ZZZZZZZZZZZZZZZZ";
END IF;
END PROCESS;
END datpatharch;[/CODE]

[QUOTE=science_man_88;422883]you are already on the 7th line by the time something even remotely close sounding comes up. I was going to go over potential structure we could use but what ever.[/QUOTE]

My bad - I mixed up the refrain with the opening ... perhaps because imagining a bunch of white people loudly singing about Canada as their 'native land' induces cognitive dissonance.

Back to the original off-topic ... suggest you ask user mancoast for timings of his spiffy 'sm88-mul' code on (say) a 70-mbit input, and then see if you double the speed via some of the optimizations you mentioned.

[QUOTE=ewmayer;422926]My bad - I mixed up the refrain with the opening ... perhaps because imagining a bunch of white people loudly singing about Canada as their 'native land' induces cognitive dissonance.[/QUOTE]

Hey!

At least Canadians never imported slaves.

[QUOTE=ewmayer;422860]I suppose a national anthem whose wording opens with "Oh, Canada! [B][U]We stand on cars and freeze..[/U][/B]." is rather a big tip-off, innit?[/QUOTE]

:fusion:
Good one ... I resemble that remark.

[QUOTE=chalsall;422930]Hey!

At least Canadians never imported slaves.[/QUOTE]

You [url=https://en.wikipedia.org/wiki/Slavery_in_Canada]sure[/url] about that? (Clearly at a drastically lesser level than their southern neighbo(u)r, obviously.)

OTOH they did name one of their [url=https://en.wikipedia.org/wiki/Great_Slave_Lake]notable lakes[/url] in homage to the practice (in this case, as practiced by a native tribe). Petrw1, that's kinda/sorta in your neck of the, um, plains, yes? (Just a short 1000-mile - sorry, 1600-km - drive NW and you're there.)

[QUOTE=ewmayer;422932]You [url=https://en.wikipedia.org/wiki/Slavery_in_Canada]sure[/url] about that? (Clearly at a drastically lesser level than their southern neighbo(u)r, obviously.)

OTOH they did name one of their [url=https://en.wikipedia.org/wiki/Great_Slave_Lake]notable lakes[/url] in homage to the practice (in this case, as practiced by a native tribe). Petrw1, that's kinda/sorta in your neck of the, um, plains, yes? (Just a short 1000-mile - sorry, 1600-km - drive NW and you're there.)[/QUOTE]

They also have an island in a lake on an island in a lake [url]https://www.google.com.au/maps/place/Canada/@51.3506826,-68.7968159,2001m/data=!3m1!1e3!4m2!3m1!1s0x4b0d03d337cc6ad9:0x9968b72aa2438fa5!6m1!1e1[/url]