[QUOTE=Mini-Geek;286736]Using [spoiler] doesn't really hide your assignment keys or exponents. All someone needs to do is select the text (or be a bot, which doesn't care about silly things like black-on-black text).[/QUOTE]
[QUOTE=Dubslow]Indeed, but I don't think there's anybody nefarious who would read those posts. And what's the worst they could do, steal a few hundred GD of credit? After I've already completed them? :lol:[/QUOTE]
[COLOR="PaleTurquoise"].[/COLOR]

[QUOTE=Dubslow;286746]Indeed, but I don't think there's anybody nefarious who would read those posts. And what's the worst they could do, steal a few hundred GD of credit? After I've already completed them? :lol:[COLOR=PaleTurquoise].[/COLOR][/QUOTE]The worst that can happen includes reinforcing a bad habit, which someday might make a big difference when it really does matter.

There was no need to redact the AID out since it was not valid in the first place, which was the point of the original posting... :no:

[QUOTE=KyleAskine;286737]I turned off communication with PrimeNet for the time being on my Linux box, out of immense frustration.[/QUOTE]

That's weird.

My understanding is (or, at least, was) that Prime95 / mprime would not remove an assignment from worktodo.txt if it had had any work done on it.

George: thoughts?

[QUOTE=chalsall;286791]That's weird.

My understanding is (or, at least, was) that Prime95 / mprime would not remove an assignment from worktodo.txt if it had had any work done on it.

George: thoughts?[/QUOTE]

No work had been done on them. My LL is just nearing completion, so it was time to queue up more work. I guess it just hated the P-1's I had and decided to give me another LL instead.

This has never happened in the past. I made sure to shutdown before altering worktodo.txt. Prime95 has had no issues, only mprime.

[QUOTE=chalsall;286791]That's weird.

My understanding is (or, at least, was) that Prime95 / mprime would not remove an assignment from worktodo.txt if it had had any work done on it.

George: thoughts?[/QUOTE]

I have no idea what is going on. It shouldn't happen.

sFFT: Sparse Fast Fourier Transform
 

George, let me ask you question on the topic which I'm incompetent in. Does recent research on Sparse Fast Fourier Transform algorithm by MIT make any sense for Prime95?
[url]http://www.i-programmer.info/news/181-algorithms/3644-a-faster-fourier-transform.html[/url]
[url]http://groups.csail.mit.edu/netmit/sFFT/[/url]

[QUOTE=clarke;286895]George, let me ask you question on the topic which I'm incompetent in. Does recent research on Sparse Fast Fourier Transform algorithm by MIT make any sense for Prime95?[/QUOTE]

It is useless. Prime95's FFTs are not sparse and even if it were you cannot discard the sparse data as the loss of even a single bit of information ruins the calculations.

An example of both ht HT detector (recently discussed concerning Bdot) and how mprime -c does not appear to be contacting the server. Auto. comm. is off, as I mentioned above.
[code]bill@Gravemind:~∰∂ mprime -c
[Main thread Jan 22 14:41] Mersenne number primality test program version 26.6
[Main thread Jan 22 14:41:02] Optimizing for CPU architecture: Core i3/i5/i7, L2 cache size: 256 KB, L3 cache size: 8 MB
[Main thread Jan 22 14:41:02] Unable to detect some of the hyperthreaded logical CPUs.
[Main thread Jan 22 14:41:02] Enough information obtained to make a reasonable guess.
[Main thread Jan 22 14:41:02] Logical CPUs 1,5 form one physical CPU.
[Main thread Jan 22 14:41:02] Logical CPUs 2,6 form one physical CPU.
[Main thread Jan 22 14:41:02] Logical CPUs 3,7 form one physical CPU.
[Main thread Jan 22 14:41:02] Logical CPUs 4,8 form one physical CPU.
bill@Gravemind:~∰∂ mprime -c
[Main thread Jan 22 14:41] Mersenne number primality test program version 26.6
[Main thread Jan 22 14:41:14] Optimizing for CPU architecture: Core i3/i5/i7, L2 cache size: 256 KB, L3 cache size: 8 MB
[Main thread Jan 22 14:41:14] Logical CPUs 1,7 form one physical CPU.
[Main thread Jan 22 14:41:14] Logical CPUs 2,3 form one physical CPU.
[Main thread Jan 22 14:41:14] Logical CPUs 4,8 form one physical CPU.
[Main thread Jan 22 14:41:14] Logical CPUs 5,6 form one physical CPU.
bill@Gravemind:~∰∂ mprime -c
[Main thread Jan 22 14:41] Mersenne number primality test program version 26.6
[Main thread Jan 22 14:41:16] Optimizing for CPU architecture: Core i3/i5/i7, L2 cache size: 256 KB, L3 cache size: 8 MB
[Main thread Jan 22 14:41:16] Unable to detect some of the hyperthreaded logical CPUs.
[Main thread Jan 22 14:41:16] Enough information obtained to make a reasonable guess.
[Main thread Jan 22 14:41:16] Logical CPUs 1,5 form one physical CPU.
[Main thread Jan 22 14:41:16] Logical CPUs 2,6 form one physical CPU.
[Main thread Jan 22 14:41:16] Logical CPUs 3,7 form one physical CPU.
[Main thread Jan 22 14:41:16] Logical CPUs 4,8 form one physical CPU.
bill@Gravemind:~∰∂ mprime -c
[Main thread Jan 22 14:41] Mersenne number primality test program version 26.6
[Main thread Jan 22 14:41:20] Optimizing for CPU architecture: Core i3/i5/i7, L2 cache size: 256 KB, L3 cache size: 8 MB
[Main thread Jan 22 14:41:20] Logical CPUs 1,5 form one physical CPU.
[Main thread Jan 22 14:41:20] Logical CPUs 2,6 form one physical CPU.
[Main thread Jan 22 14:41:20] Logical CPUs 3,7 form one physical CPU.
[Main thread Jan 22 14:41:20] Logical CPUs 4,8 form one physical CPU.
bill@Gravemind:~∰∂ mprime -c
[Main thread Jan 22 14:41] Mersenne number primality test program version 26.6
[Main thread Jan 22 14:41:21] Optimizing for CPU architecture: Core i3/i5/i7, L2 cache size: 256 KB, L3 cache size: 8 MB
[Main thread Jan 22 14:41:21] Logical CPUs 1,5 form one physical CPU.
[Main thread Jan 22 14:41:21] Logical CPUs 2,6 form one physical CPU.
[Main thread Jan 22 14:41:21] Logical CPUs 3,7 form one physical CPU.
[Main thread Jan 22 14:41:21] Logical CPUs 4,8 form one physical CPU.
bill@Gravemind:~∰∂ mprime -c
[Main thread Jan 22 14:41] Mersenne number primality test program version 26.6
[Main thread Jan 22 14:41:22] Optimizing for CPU architecture: Core i3/i5/i7, L2 cache size: 256 KB, L3 cache size: 8 MB
[Main thread Jan 22 14:41:22] Logical CPUs 1,3 form one physical CPU.
[Main thread Jan 22 14:41:22] Logical CPUs 2,6 form one physical CPU.
[Main thread Jan 22 14:41:22] Logical CPUs 4,5 form one physical CPU.
[Main thread Jan 22 14:41:22] Logical CPUs 7,8 form one physical CPU.
bill@Gravemind:~∰∂ mprime -c
[Main thread Jan 22 14:41] Mersenne number primality test program version 26.6
[Main thread Jan 22 14:41:23] Optimizing for CPU architecture: Core i3/i5/i7, L2 cache size: 256 KB, L3 cache size: 8 MB
[Main thread Jan 22 14:41:23] Logical CPUs 1,3 form one physical CPU.
[Main thread Jan 22 14:41:23] Logical CPUs 2,6 form one physical CPU.
[Main thread Jan 22 14:41:23] Logical CPUs 4,8 form one physical CPU.
[Main thread Jan 22 14:41:23] Logical CPUs 5,7 form one physical CPU.
bill@Gravemind:~∰∂ mprime -c
[Main thread Jan 22 14:41] Mersenne number primality test program version 26.6
[Main thread Jan 22 14:41:24] Optimizing for CPU architecture: Core i3/i5/i7, L2 cache size: 256 KB, L3 cache size: 8 MB
[Main thread Jan 22 14:41:24] Unable to detect some of the hyperthreaded logical CPUs.
[Main thread Jan 22 14:41:24] Assuming logical CPUs 1 and 2, 3 and 4, etc. are each from one physical CPU core.
[Main thread Jan 22 14:41:24] To the best of my knowledge this assumption is only valid for Microsoft Windows.
[Main thread Jan 22 14:41:24] To override this assumption, see AffinityScramble2 in undoc.txt.
bill@Gravemind:~∰∂ mprime -c
[Main thread Jan 22 14:41] Mersenne number primality test program version 26.6
[Main thread Jan 22 14:41:29] Optimizing for CPU architecture: Core i3/i5/i7, L2 cache size: 256 KB, L3 cache size: 8 MB
[Main thread Jan 22 14:41:29] Unable to detect some of the hyperthreaded logical CPUs.
[Main thread Jan 22 14:41:29] Enough information obtained to make a reasonable guess.
[Main thread Jan 22 14:41:29] Logical CPUs 1,5 form one physical CPU.
[Main thread Jan 22 14:41:29] Logical CPUs 2,6 form one physical CPU.
[Main thread Jan 22 14:41:29] Logical CPUs 3,7 form one physical CPU.
[Main thread Jan 22 14:41:29] Logical CPUs 4,8 form one physical CPU.
bill@Gravemind:~∰∂ [/code]

[QUOTE=Dubslow;286968]An example of both ht HT detector (recently discussed concerning Bdot) and how mprime -c does not appear to be contacting the server. Auto. comm. is off, as I mentioned above.
[/QUOTE]
You mentioned earlier that you've set PrimeNet=0, which will disable any communication (only manual submit form will work). Set ManualComm=1 (and PrimeNet=1) to allow mprime -c to communicate.
Note, the results created while PrimeNet=0 will not be sent to the server, even after re-enabling PrimeNet. You'll need to use the manual results page for them.

I figured both of those out the hard way. (Thanks though :smile:) The only difference is that when PrimeNet=1 and MC=0, it will report old results that had an AID, but I had to manually report those without.


Also, can someone explain why when I use the AdvancedTest, it automatically tries to reserve it with PrimeNet? (I use AdvancedTest specifically when I'm not going through PrimeNet, otherwise I'd just use Test.)