RC5-64 project completed
 

Now that the above is finally resolved, is there any estimate on the increase of processing power to be contributed to GIMPS, from people switching over?

Michael

I would hope so :)

That project is really waste of time.... Absolutely NOTHING is gained by completing it.

Most dnet clients will revert to OGR... That is the default configuration...

One can't help but wonder how many thousands of corporate borgs are out there that will never be updated because the dude that installed the client is long gone or has forgotten about it...

While I agree that RC5-64 was a waste, and I do hope RC5-72 is scrapped, some people really enjoyed running it, so we must be a bit tolerant... I know that Mac users have no other project that runs really well on their boxes... On the Mac I had, it was maybe 4x faster than any x86 box was... And my Mac was just a SP 933MHz G4... But on any other project it was very sad...

Supposedly, there are special Altivec enhancements for FFTs, but I am not a programmer...

http://developer.apple.com/hardware/ve/pdf/g4fft.pdf

I do know that glucas is a wonderfully designed program but it is just too slow to be worth using (IMO)... I'd be inclined to do a work swap with someone who has a P4...

Unless you win it! Even then, just a $1K award. Now that $50K 10M digit prime award... let's see about that.

Michael


[quote="xtreme2k"]I would hope so :)

That project is really waste of time.... Absolutely NOTHING is gained by completing it.[/quote]

On RC5, the G4 was appx. 3x faster *per clock* than an Athlon, a hair more than that vs. a P-III.

Down side - for the cost of a dual G4-500 box, I could EASILY build a dual Athlon XP2000+ box that would run faster than the G4 box even on RC5-64 - and have enough money left over to build a single XP2000+ box as well.

I was presuming *used* G4 parts vs. *new* Athlon parts too - local Uni Surplus place has a buncha PCI Power Macs that were VERY cheap, and easy to upgrade to G4.

Does Altavec support high-enough precision floating point ops to even be usable on Prime?

[quote="QuintLeo"]On RC5, the G4 was appx. 3x faster *per clock* than an Athlon, a hair more than that vs. a P-III.
[/quote]

They could've probably gained a similar speedup on the Pentium by using
MMX's SIMD funtionality, which is in many ways similar to AltiVec.
(Although I don't believe MMX has quite the same amount of flexibility
when it comes to SIMD operations on integers - AV can do 16-way ops on
groups of 16 8-bit ints, 8-way on 8x16-bit and 4-way on 4x32.)

I suspect a mac-ophile RC5er did the AV stuff and there was no analogous
effort to write code for MMX.

[quote]
Does Altavec support high-enough precision floating point ops to even be usable on Prime?[/quote]

Neither AltiVec nor MMX have sufficient floating precision to be of much
use - 32-bit floats just don't cut it here. And AltiVec doesn't support SSE2.

-Ernst

I tried some of the other projects on my G4/800. OGR was the only thing that flew, faster than many Ghz machines. Seti ran about 9 hours with the benchmark WU.

Glucas is running .113 iteration on an 7xxxxxx DC exponent, it's around a P3/600mhz in comparison. That's good enough for me. :-) :-)

I was looking for some factoring code that would work with the Primet manual pages for the Mac, I haven't found any yet. With the 1Mb L3 cache, it may run quite well on factoring.

The RC5 client *did* add a Pentium MMX optimised core - it added appx. 40% to the Pentium-MMX keyrate when it was introduced, over the previous best core for the Pentium.

This brought my P166-MMX up to about 90% of the keyrate of my K5-PR166 (which actually clocks at 117.5 Mhz) - 345-350kkeys/sec or so vs. 390kkeys/sec.

Enhancements added to later Pentiums blew the MMX core out of the water entirely - it's still THERE, but it's a lot SLOWER on P-Pro and later CPUs.

ref http//n0cgi.distributed.net/faq/cache/264.html - it's a little dated, but gives some handy data.

I believe the primary problem with the P5-class Pentiums is that they did not support a hardware rotate instruction - the K6 also did rotate in microcode, and ended up running a LOT slower than a K5 per clock as a result (K6-233 was slower OUTRIGHT than a K5-PR166 on RC5, IIRC - despite having almost *twice* the actual clock rate).

ref http//n0cgi.distributed.net/faq/cache/55.html

The P-III and Athlon definitely support hardware rotate - they're a hair FASTER than a K5 per clock on RC5 - the P-IV went back to microcode for that.

The way RC5 is implimented, rotate is *the* key instruction. I suspect each individual Altivec "processing line" in a G4 is a lot slower than K5/Athlon/P-III cpus at RC5 - but the G4 wins out by having so MANY of those processing lines in parallel.

Do I recall correctly that IBM's next PowerPC CPU is supposed to have *dual* Altivecs units?