Compiling GNFS sievers on AArch64 platform
 

I'm working on getting the gnfs-lasieve binaries built for an RPi Model 3B. I am, however, getting stumped at the first step. Running
[CODE] make liblasieve.a[/CODE] gives a host of "Error: unknown mnemonic" errors. gcc -v returns [CODE]Using built-in specs.
COLLECT_GCC=/usr/aarch64-unknown-linux-gnu/gcc-bin/5.4.0/gcc
COLLECT_LTO_WRAPPER=/usr/libexec/gcc/aarch64-unknown-linux-gnu/5.4.0/lto-wrapper
Target: aarch64-unknown-linux-gnu
Configured with: /var/tmp/portage/sys-devel/gcc-5.4.0-r3/work/gcc-5.4.0/configure --host=aarch64-unknown-linux-gnu --build=aarch64-unknown-linux-gnu --prefix=/usr --bindir=/usr/aarch64-unknown-linux-gnu/gcc-bin/5.4.0 --includedir=/usr/lib/gcc/aarch64-unknown-linux-gnu/5.4.0/include --datadir=/usr/share/gcc-data/aarch64-unknown-linux-gnu/5.4.0 --mandir=/usr/share/gcc-data/aarch64-unknown-linux-gnu/5.4.0/man --infodir=/usr/share/gcc-data/aarch64-unknown-linux-gnu/5.4.0/info --with-gxx-include-dir=/usr/lib/gcc/aarch64-unknown-linux-gnu/5.4.0/include/g++-v5 --with-python-dir=/share/gcc-data/aarch64-unknown-linux-gnu/5.4.0/python --enable-languages=c,c++,fortran --enable-obsolete --enable-secureplt --disable-werror --with-system-zlib --enable-nls --without-included-gettext --enable-checking=release --with-bugurl=https://bugs.gentoo.org/ --with-pkgversion='Gentoo 5.4.0-r3 p1.3, pie-0.6.5' --enable-libstdcxx-time --enable-shared --enable-threads=posix --enable-__cxa_atexit --enable-clocale=gnu --enable-multilib --disable-altivec --disable-fixed-point --disable-libgcj --enable-libgomp --disable-libmudflap --disable-libssp --disable-libcilkrts --disable-libmpx --disable-vtable-verify --disable-libvtv --enable-lto --without-isl --disable-libsanitizer
Thread model: posix
gcc version 5.4.0 (Gentoo 5.4.0-r3 p1.3, pie-0.6.5)[/CODE]

64-bit compilations of GMP and GMP-ECM completed without any issues at all, so I don't see any issues with the compiler itself. Can someone suggest a first step here?

I would run [c]./configure[/c] if it exists. Then inspect Makefile to see what tartgets are available like "all:" so that you can, in this case, run [c]make all[/c] :smile:

Would that I could. This is the 64-bit assembly experimental lasieve binaries. The instructions are as follows:
[CODE]
follow these steps to build the binaries on a 64-bit machine.
These should build and run on Athlon64, or Core2 cpus.

******************************
NOTE for Phenom/K8 users: replace in athlon64/ls-defs.asm
define(l1_bits,15)dnl
=>
define(l1_bits,16)dnl

and in athlon64/siever-config.h
#define L1_BITS 15
=>
#define L1_BITS 16

This may add 5-10% speed to your sieving speed.
But try it both ways and decide for yourself. Caveat emptor!
******************************

Prerequisites: gmp.h libgmp

cd athlon64
make liblasieve.a
make liblasieveI11.a
make liblasieveI12.a
make liblasieveI13.a
make liblasieveI14.a
make liblasieveI15.a
make liblasieveI16.a
cp *.a ..
cd ..
ln -s athlon64 asm
make
[/CODE]

The assembly errors come from running any of the make commands listed. liblasieve.a fails trying to compile the pt64.s assembly file.

[QUOTE=wombatman;454258]liblasieve.a fails trying to compile the pt64.s assembly file.[/QUOTE]I don't have any of the files on my system so take what I say as probably useless. But does the pt64.s file have x86-64 instructions, or AArch64 instructions? If the former then you'll have to rewrite it. If the latter then it might just be a configuration error.

ETA: Showing us the actual error messages would probably help us to understand what went wrong.

[QUOTE=retina;454268]I don't have any of the files on my system so take what I say as probably useless. But does the pt64.s file have x86-64 instructions, or AArch64 instructions? If the former then you'll have to rewrite it. If the latter then it might just be a configuration error.

ETA: Showing us the actual error messages would probably help us to understand what went wrong.[/QUOTE]

Here's a few of the errors (there are ~2 dozen, so I won't put them all):

[CODE]pt64.s:7: Error: unknown mnemonic `movq' -- `movq %r11,%rax'
pt64.s:8: Error: unknown mnemonic `mulq' -- `mulq %r11'
pt64.s:9: Error: unknown mnemonic `movq' -- `movq %rdx,%r11'
pt64.s:10: Error: unknown mnemonic `mulq' -- `mulq %r8'
pt64.s:11: Error: unknown mnemonic `mulq' -- `mulq %rdi'
pt64.s:12: Error: unknown mnemonic `xorq' -- `xorq %rax,%rax'
pt64.s:13: Error: unknown mnemonic `subq' -- `subq %rdx,%r11'[/CODE]

I'm thinking you're right that it's x86-64 code that will need to be converted, but I'll have a look a bit later.

[QUOTE=wombatman;454281]Here's a few of the errors (there are ~2 dozen, so I won't put them all):

[CODE]pt64.s:7: Error: unknown mnemonic `movq' -- `movq %r11,%rax'
pt64.s:8: Error: unknown mnemonic `mulq' -- `mulq %r11'
pt64.s:9: Error: unknown mnemonic `movq' -- `movq %rdx,%r11'
pt64.s:10: Error: unknown mnemonic `mulq' -- `mulq %r8'
pt64.s:11: Error: unknown mnemonic `mulq' -- `mulq %rdi'
pt64.s:12: Error: unknown mnemonic `xorq' -- `xorq %rax,%rax'
pt64.s:13: Error: unknown mnemonic `subq' -- `subq %rdx,%r11'[/CODE]

I'm thinking you're right that it's x86-64 code that will need to be converted, but I'll have a look a bit later.[/QUOTE]Yes indeed. rax, rdx, rdi. Definitely not AArch64. You'll need x0, x1, w0, w1, ...

Ok. Looks like I have a challenge then. :smile:

Thanks for confirming it.

The GGNFS codebase should have a 'make generic' option in the makefile that would ignore all the assembly language. Maybe that applies to the sievers too.

[QUOTE=jasonp;454366]The GGNFS codebase should have a 'make generic' option in the makefile that would ignore all the assembly language. Maybe that applies to the sievers too.[/QUOTE]

It does have something along those lines (I think it was the x86 option). I used that to build the 32-bit version of the sievers, but I'm looking to building the 64-bit ones as well. I'll have to double-check whether there's a generic version of those.

I've been looking at various resources to try and understand assembly generally and the differences between x64 and aarch64 assembly. One bit I'm not understanding is the following--in pt64.s, the first line of the modsq64 function is:

[CODE] movq %r11,%rax[/CODE]

Now, my reading makes clear that this is copying a quad word (so, 64 bits) from register 11 to register a extended (or the accumulating register?). Now, my question is: is there something special about r11? Could it just as easily be "movq %r12, %rax" instead?

[QUOTE=wombatman;454661]Now, my question is: is there something special about r11? Could it just as easily be "movq %r12, %rax" instead?[/QUOTE]You can freely choose any registers with MOV. R11 has no special functionality, it is just another register. For that matter, RAX has no special functionality, it is just another register also. But there are some special instructions that target particular registers, e.g LODSQ will target RAX and source from RSI.